mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199855 91177308-0d34-0410-b5e6-96231b3b80d8
818 lines
28 KiB
C++
818 lines
28 KiB
C++
//===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the X86 Disassembler.
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// It contains code to translate the data produced by the decoder into
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// MCInsts.
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// Documentation for the disassembler can be found in X86Disassembler.h.
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//
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//===----------------------------------------------------------------------===//
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#include "X86Disassembler.h"
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#include "X86DisassemblerDecoder.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDisassembler.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MemoryObject.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#define GET_REGINFO_ENUM
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#include "X86GenRegisterInfo.inc"
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#define GET_INSTRINFO_ENUM
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#include "X86GenInstrInfo.inc"
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#define GET_SUBTARGETINFO_ENUM
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#include "X86GenSubtargetInfo.inc"
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using namespace llvm;
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using namespace llvm::X86Disassembler;
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void x86DisassemblerDebug(const char *file,
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unsigned line,
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const char *s) {
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dbgs() << file << ":" << line << ": " << s;
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}
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const char *x86DisassemblerGetInstrName(unsigned Opcode, const void *mii) {
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const MCInstrInfo *MII = static_cast<const MCInstrInfo *>(mii);
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return MII->getName(Opcode);
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}
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#define debug(s) DEBUG(x86DisassemblerDebug(__FILE__, __LINE__, s));
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namespace llvm {
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// Fill-ins to make the compiler happy. These constants are never actually
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// assigned; they are just filler to make an automatically-generated switch
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// statement work.
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namespace X86 {
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enum {
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BX_SI = 500,
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BX_DI = 501,
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BP_SI = 502,
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BP_DI = 503,
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sib = 504,
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sib64 = 505
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};
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}
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extern Target TheX86_32Target, TheX86_64Target;
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}
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static bool translateInstruction(MCInst &target,
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InternalInstruction &source,
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const MCDisassembler *Dis);
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X86GenericDisassembler::X86GenericDisassembler(const MCSubtargetInfo &STI,
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const MCInstrInfo *MII)
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: MCDisassembler(STI), MII(MII) {
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switch (STI.getFeatureBits() &
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(X86::Mode16Bit | X86::Mode32Bit | X86::Mode64Bit)) {
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case X86::Mode16Bit:
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fMode = MODE_16BIT;
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break;
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case X86::Mode32Bit:
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fMode = MODE_32BIT;
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break;
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case X86::Mode64Bit:
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fMode = MODE_64BIT;
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break;
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default:
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llvm_unreachable("Invalid CPU mode");
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}
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}
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X86GenericDisassembler::~X86GenericDisassembler() {
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delete MII;
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}
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/// regionReader - a callback function that wraps the readByte method from
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/// MemoryObject.
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///
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/// @param arg - The generic callback parameter. In this case, this should
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/// be a pointer to a MemoryObject.
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/// @param byte - A pointer to the byte to be read.
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/// @param address - The address to be read.
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static int regionReader(const void* arg, uint8_t* byte, uint64_t address) {
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const MemoryObject* region = static_cast<const MemoryObject*>(arg);
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return region->readByte(address, byte);
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}
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/// logger - a callback function that wraps the operator<< method from
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/// raw_ostream.
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///
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/// @param arg - The generic callback parameter. This should be a pointe
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/// to a raw_ostream.
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/// @param log - A string to be logged. logger() adds a newline.
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static void logger(void* arg, const char* log) {
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if (!arg)
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return;
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raw_ostream &vStream = *(static_cast<raw_ostream*>(arg));
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vStream << log << "\n";
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}
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//
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// Public interface for the disassembler
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//
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MCDisassembler::DecodeStatus
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X86GenericDisassembler::getInstruction(MCInst &instr,
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uint64_t &size,
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const MemoryObject ®ion,
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uint64_t address,
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raw_ostream &vStream,
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raw_ostream &cStream) const {
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CommentStream = &cStream;
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InternalInstruction internalInstr;
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dlog_t loggerFn = logger;
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if (&vStream == &nulls())
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loggerFn = 0; // Disable logging completely if it's going to nulls().
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int ret = decodeInstruction(&internalInstr,
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regionReader,
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(const void*)®ion,
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loggerFn,
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(void*)&vStream,
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(const void*)MII,
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address,
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fMode);
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if (ret) {
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size = internalInstr.readerCursor - address;
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return Fail;
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}
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else {
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size = internalInstr.length;
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return (!translateInstruction(instr, internalInstr, this)) ?
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Success : Fail;
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}
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}
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//
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// Private code that translates from struct InternalInstructions to MCInsts.
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//
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/// translateRegister - Translates an internal register to the appropriate LLVM
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/// register, and appends it as an operand to an MCInst.
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///
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/// @param mcInst - The MCInst to append to.
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/// @param reg - The Reg to append.
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static void translateRegister(MCInst &mcInst, Reg reg) {
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#define ENTRY(x) X86::x,
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uint8_t llvmRegnums[] = {
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ALL_REGS
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0
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};
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#undef ENTRY
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uint8_t llvmRegnum = llvmRegnums[reg];
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mcInst.addOperand(MCOperand::CreateReg(llvmRegnum));
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}
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/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
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/// immediate Value in the MCInst.
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///
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/// @param Value - The immediate Value, has had any PC adjustment made by
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/// the caller.
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/// @param isBranch - If the instruction is a branch instruction
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/// @param Address - The starting address of the instruction
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/// @param Offset - The byte offset to this immediate in the instruction
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/// @param Width - The byte width of this immediate in the instruction
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///
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/// If the getOpInfo() function was set when setupForSymbolicDisassembly() was
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/// called then that function is called to get any symbolic information for the
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/// immediate in the instruction using the Address, Offset and Width. If that
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/// returns non-zero then the symbolic information it returns is used to create
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/// an MCExpr and that is added as an operand to the MCInst. If getOpInfo()
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/// returns zero and isBranch is true then a symbol look up for immediate Value
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/// is done and if a symbol is found an MCExpr is created with that, else
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/// an MCExpr with the immediate Value is created. This function returns true
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/// if it adds an operand to the MCInst and false otherwise.
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static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
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uint64_t Address, uint64_t Offset,
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uint64_t Width, MCInst &MI,
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const MCDisassembler *Dis) {
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return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
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Offset, Width);
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}
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/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
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/// referenced by a load instruction with the base register that is the rip.
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/// These can often be addresses in a literal pool. The Address of the
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/// instruction and its immediate Value are used to determine the address
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/// being referenced in the literal pool entry. The SymbolLookUp call back will
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/// return a pointer to a literal 'C' string if the referenced address is an
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/// address into a section with 'C' string literals.
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static void tryAddingPcLoadReferenceComment(uint64_t Address, uint64_t Value,
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const void *Decoder) {
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const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
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Dis->tryAddingPcLoadReferenceComment(Value, Address);
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}
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static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = {
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0, // SEG_OVERRIDE_NONE
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X86::CS,
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X86::SS,
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X86::DS,
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X86::ES,
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X86::FS,
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X86::GS
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};
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/// translateSrcIndex - Appends a source index operand to an MCInst.
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///
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/// @param mcInst - The MCInst to append to.
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/// @param insn - The internal instruction.
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static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) {
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unsigned baseRegNo;
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if (insn.mode == MODE_64BIT)
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baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::RSI;
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else if (insn.mode == MODE_32BIT)
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baseRegNo = insn.prefixPresent[0x67] ? X86::SI : X86::ESI;
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else {
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assert(insn.mode == MODE_16BIT);
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baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::SI;
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}
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MCOperand baseReg = MCOperand::CreateReg(baseRegNo);
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mcInst.addOperand(baseReg);
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MCOperand segmentReg;
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segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
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mcInst.addOperand(segmentReg);
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return false;
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}
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/// translateDstIndex - Appends a destination index operand to an MCInst.
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///
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/// @param mcInst - The MCInst to append to.
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/// @param insn - The internal instruction.
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static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn) {
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unsigned baseRegNo;
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if (insn.mode == MODE_64BIT)
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baseRegNo = insn.prefixPresent[0x67] ? X86::EDI : X86::RDI;
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else if (insn.mode == MODE_32BIT)
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baseRegNo = insn.prefixPresent[0x67] ? X86::DI : X86::EDI;
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else {
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assert(insn.mode == MODE_16BIT);
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baseRegNo = insn.prefixPresent[0x67] ? X86::EDI : X86::DI;
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}
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MCOperand baseReg = MCOperand::CreateReg(baseRegNo);
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mcInst.addOperand(baseReg);
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return false;
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}
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/// translateImmediate - Appends an immediate operand to an MCInst.
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///
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/// @param mcInst - The MCInst to append to.
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/// @param immediate - The immediate value to append.
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/// @param operand - The operand, as stored in the descriptor table.
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/// @param insn - The internal instruction.
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static void translateImmediate(MCInst &mcInst, uint64_t immediate,
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const OperandSpecifier &operand,
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InternalInstruction &insn,
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const MCDisassembler *Dis) {
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// Sign-extend the immediate if necessary.
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OperandType type = (OperandType)operand.type;
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bool isBranch = false;
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uint64_t pcrel = 0;
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if (type == TYPE_RELv) {
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isBranch = true;
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pcrel = insn.startLocation +
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insn.immediateOffset + insn.immediateSize;
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switch (insn.displacementSize) {
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default:
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break;
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case 1:
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if(immediate & 0x80)
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immediate |= ~(0xffull);
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break;
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case 2:
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if(immediate & 0x8000)
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immediate |= ~(0xffffull);
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break;
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case 4:
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if(immediate & 0x80000000)
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immediate |= ~(0xffffffffull);
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break;
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case 8:
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break;
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}
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}
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// By default sign-extend all X86 immediates based on their encoding.
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else if (type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 ||
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type == TYPE_IMM64) {
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uint32_t Opcode = mcInst.getOpcode();
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switch (operand.encoding) {
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default:
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break;
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case ENCODING_IB:
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// Special case those X86 instructions that use the imm8 as a set of
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// bits, bit count, etc. and are not sign-extend.
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if (Opcode != X86::BLENDPSrri && Opcode != X86::BLENDPDrri &&
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Opcode != X86::PBLENDWrri && Opcode != X86::MPSADBWrri &&
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Opcode != X86::DPPSrri && Opcode != X86::DPPDrri &&
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Opcode != X86::INSERTPSrr && Opcode != X86::VBLENDPSYrri &&
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Opcode != X86::VBLENDPSYrmi && Opcode != X86::VBLENDPDYrri &&
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Opcode != X86::VBLENDPDYrmi && Opcode != X86::VPBLENDWrri &&
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Opcode != X86::VMPSADBWrri && Opcode != X86::VDPPSYrri &&
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Opcode != X86::VDPPSYrmi && Opcode != X86::VDPPDrri &&
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Opcode != X86::VINSERTPSrr)
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if(immediate & 0x80)
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immediate |= ~(0xffull);
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break;
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case ENCODING_IW:
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if(immediate & 0x8000)
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immediate |= ~(0xffffull);
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break;
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case ENCODING_ID:
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if(immediate & 0x80000000)
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immediate |= ~(0xffffffffull);
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break;
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case ENCODING_IO:
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break;
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}
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}
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switch (type) {
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case TYPE_XMM32:
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case TYPE_XMM64:
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case TYPE_XMM128:
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mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4)));
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return;
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case TYPE_XMM256:
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mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4)));
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return;
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case TYPE_XMM512:
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mcInst.addOperand(MCOperand::CreateReg(X86::ZMM0 + (immediate >> 4)));
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return;
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case TYPE_REL8:
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isBranch = true;
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pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize;
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if(immediate & 0x80)
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immediate |= ~(0xffull);
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break;
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case TYPE_REL32:
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case TYPE_REL64:
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isBranch = true;
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pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize;
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if(immediate & 0x80000000)
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immediate |= ~(0xffffffffull);
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break;
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default:
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// operand is 64 bits wide. Do nothing.
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break;
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}
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if(!tryAddingSymbolicOperand(immediate + pcrel, isBranch, insn.startLocation,
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insn.immediateOffset, insn.immediateSize,
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mcInst, Dis))
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mcInst.addOperand(MCOperand::CreateImm(immediate));
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if (type == TYPE_MOFFS8 || type == TYPE_MOFFS16 ||
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type == TYPE_MOFFS32 || type == TYPE_MOFFS64) {
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MCOperand segmentReg;
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segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
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mcInst.addOperand(segmentReg);
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}
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}
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/// translateRMRegister - Translates a register stored in the R/M field of the
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/// ModR/M byte to its LLVM equivalent and appends it to an MCInst.
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/// @param mcInst - The MCInst to append to.
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/// @param insn - The internal instruction to extract the R/M field
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/// from.
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/// @return - 0 on success; -1 otherwise
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static bool translateRMRegister(MCInst &mcInst,
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InternalInstruction &insn) {
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if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
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debug("A R/M register operand may not have a SIB byte");
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return true;
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}
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switch (insn.eaBase) {
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default:
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debug("Unexpected EA base register");
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return true;
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case EA_BASE_NONE:
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debug("EA_BASE_NONE for ModR/M base");
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return true;
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#define ENTRY(x) case EA_BASE_##x:
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ALL_EA_BASES
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#undef ENTRY
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debug("A R/M register operand may not have a base; "
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"the operand must be a register.");
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return true;
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#define ENTRY(x) \
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case EA_REG_##x: \
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mcInst.addOperand(MCOperand::CreateReg(X86::x)); break;
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ALL_REGS
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#undef ENTRY
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}
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return false;
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}
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/// translateRMMemory - Translates a memory operand stored in the Mod and R/M
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/// fields of an internal instruction (and possibly its SIB byte) to a memory
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/// operand in LLVM's format, and appends it to an MCInst.
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///
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/// @param mcInst - The MCInst to append to.
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/// @param insn - The instruction to extract Mod, R/M, and SIB fields
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/// from.
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/// @return - 0 on success; nonzero otherwise
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static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn,
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const MCDisassembler *Dis) {
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// Addresses in an MCInst are represented as five operands:
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// 1. basereg (register) The R/M base, or (if there is a SIB) the
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// SIB base
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// 2. scaleamount (immediate) 1, or (if there is a SIB) the specified
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// scale amount
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// 3. indexreg (register) x86_registerNONE, or (if there is a SIB)
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// the index (which is multiplied by the
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// scale amount)
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// 4. displacement (immediate) 0, or the displacement if there is one
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// 5. segmentreg (register) x86_registerNONE for now, but could be set
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// if we have segment overrides
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MCOperand baseReg;
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MCOperand scaleAmount;
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MCOperand indexReg;
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MCOperand displacement;
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MCOperand segmentReg;
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uint64_t pcrel = 0;
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if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
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if (insn.sibBase != SIB_BASE_NONE) {
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switch (insn.sibBase) {
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default:
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debug("Unexpected sibBase");
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return true;
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#define ENTRY(x) \
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case SIB_BASE_##x: \
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baseReg = MCOperand::CreateReg(X86::x); break;
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ALL_SIB_BASES
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#undef ENTRY
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}
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} else {
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baseReg = MCOperand::CreateReg(0);
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}
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// Check whether we are handling VSIB addressing mode for GATHER.
|
|
// If sibIndex was set to SIB_INDEX_NONE, index offset is 4 and
|
|
// we should use SIB_INDEX_XMM4|YMM4 for VSIB.
|
|
// I don't see a way to get the correct IndexReg in readSIB:
|
|
// We can tell whether it is VSIB or SIB after instruction ID is decoded,
|
|
// but instruction ID may not be decoded yet when calling readSIB.
|
|
uint32_t Opcode = mcInst.getOpcode();
|
|
bool IndexIs128 = (Opcode == X86::VGATHERDPDrm ||
|
|
Opcode == X86::VGATHERDPDYrm ||
|
|
Opcode == X86::VGATHERQPDrm ||
|
|
Opcode == X86::VGATHERDPSrm ||
|
|
Opcode == X86::VGATHERQPSrm ||
|
|
Opcode == X86::VPGATHERDQrm ||
|
|
Opcode == X86::VPGATHERDQYrm ||
|
|
Opcode == X86::VPGATHERQQrm ||
|
|
Opcode == X86::VPGATHERDDrm ||
|
|
Opcode == X86::VPGATHERQDrm);
|
|
bool IndexIs256 = (Opcode == X86::VGATHERQPDYrm ||
|
|
Opcode == X86::VGATHERDPSYrm ||
|
|
Opcode == X86::VGATHERQPSYrm ||
|
|
Opcode == X86::VGATHERDPDZrm ||
|
|
Opcode == X86::VPGATHERDQZrm ||
|
|
Opcode == X86::VPGATHERQQYrm ||
|
|
Opcode == X86::VPGATHERDDYrm ||
|
|
Opcode == X86::VPGATHERQDYrm);
|
|
bool IndexIs512 = (Opcode == X86::VGATHERQPDZrm ||
|
|
Opcode == X86::VGATHERDPSZrm ||
|
|
Opcode == X86::VGATHERQPSZrm ||
|
|
Opcode == X86::VPGATHERQQZrm ||
|
|
Opcode == X86::VPGATHERDDZrm ||
|
|
Opcode == X86::VPGATHERQDZrm);
|
|
if (IndexIs128 || IndexIs256 || IndexIs512) {
|
|
unsigned IndexOffset = insn.sibIndex -
|
|
(insn.addressSize == 8 ? SIB_INDEX_RAX:SIB_INDEX_EAX);
|
|
SIBIndex IndexBase = IndexIs512 ? SIB_INDEX_ZMM0 :
|
|
IndexIs256 ? SIB_INDEX_YMM0 : SIB_INDEX_XMM0;
|
|
insn.sibIndex = (SIBIndex)(IndexBase +
|
|
(insn.sibIndex == SIB_INDEX_NONE ? 4 : IndexOffset));
|
|
}
|
|
|
|
if (insn.sibIndex != SIB_INDEX_NONE) {
|
|
switch (insn.sibIndex) {
|
|
default:
|
|
debug("Unexpected sibIndex");
|
|
return true;
|
|
#define ENTRY(x) \
|
|
case SIB_INDEX_##x: \
|
|
indexReg = MCOperand::CreateReg(X86::x); break;
|
|
EA_BASES_32BIT
|
|
EA_BASES_64BIT
|
|
REGS_XMM
|
|
REGS_YMM
|
|
REGS_ZMM
|
|
#undef ENTRY
|
|
}
|
|
} else {
|
|
indexReg = MCOperand::CreateReg(0);
|
|
}
|
|
|
|
scaleAmount = MCOperand::CreateImm(insn.sibScale);
|
|
} else {
|
|
switch (insn.eaBase) {
|
|
case EA_BASE_NONE:
|
|
if (insn.eaDisplacement == EA_DISP_NONE) {
|
|
debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base");
|
|
return true;
|
|
}
|
|
if (insn.mode == MODE_64BIT){
|
|
pcrel = insn.startLocation +
|
|
insn.displacementOffset + insn.displacementSize;
|
|
tryAddingPcLoadReferenceComment(insn.startLocation +
|
|
insn.displacementOffset,
|
|
insn.displacement + pcrel, Dis);
|
|
baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6
|
|
}
|
|
else
|
|
baseReg = MCOperand::CreateReg(0);
|
|
|
|
indexReg = MCOperand::CreateReg(0);
|
|
break;
|
|
case EA_BASE_BX_SI:
|
|
baseReg = MCOperand::CreateReg(X86::BX);
|
|
indexReg = MCOperand::CreateReg(X86::SI);
|
|
break;
|
|
case EA_BASE_BX_DI:
|
|
baseReg = MCOperand::CreateReg(X86::BX);
|
|
indexReg = MCOperand::CreateReg(X86::DI);
|
|
break;
|
|
case EA_BASE_BP_SI:
|
|
baseReg = MCOperand::CreateReg(X86::BP);
|
|
indexReg = MCOperand::CreateReg(X86::SI);
|
|
break;
|
|
case EA_BASE_BP_DI:
|
|
baseReg = MCOperand::CreateReg(X86::BP);
|
|
indexReg = MCOperand::CreateReg(X86::DI);
|
|
break;
|
|
default:
|
|
indexReg = MCOperand::CreateReg(0);
|
|
switch (insn.eaBase) {
|
|
default:
|
|
debug("Unexpected eaBase");
|
|
return true;
|
|
// Here, we will use the fill-ins defined above. However,
|
|
// BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and
|
|
// sib and sib64 were handled in the top-level if, so they're only
|
|
// placeholders to keep the compiler happy.
|
|
#define ENTRY(x) \
|
|
case EA_BASE_##x: \
|
|
baseReg = MCOperand::CreateReg(X86::x); break;
|
|
ALL_EA_BASES
|
|
#undef ENTRY
|
|
#define ENTRY(x) case EA_REG_##x:
|
|
ALL_REGS
|
|
#undef ENTRY
|
|
debug("A R/M memory operand may not be a register; "
|
|
"the base field must be a base.");
|
|
return true;
|
|
}
|
|
}
|
|
|
|
scaleAmount = MCOperand::CreateImm(1);
|
|
}
|
|
|
|
displacement = MCOperand::CreateImm(insn.displacement);
|
|
|
|
segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
|
|
|
|
mcInst.addOperand(baseReg);
|
|
mcInst.addOperand(scaleAmount);
|
|
mcInst.addOperand(indexReg);
|
|
if(!tryAddingSymbolicOperand(insn.displacement + pcrel, false,
|
|
insn.startLocation, insn.displacementOffset,
|
|
insn.displacementSize, mcInst, Dis))
|
|
mcInst.addOperand(displacement);
|
|
mcInst.addOperand(segmentReg);
|
|
return false;
|
|
}
|
|
|
|
/// translateRM - Translates an operand stored in the R/M (and possibly SIB)
|
|
/// byte of an instruction to LLVM form, and appends it to an MCInst.
|
|
///
|
|
/// @param mcInst - The MCInst to append to.
|
|
/// @param operand - The operand, as stored in the descriptor table.
|
|
/// @param insn - The instruction to extract Mod, R/M, and SIB fields
|
|
/// from.
|
|
/// @return - 0 on success; nonzero otherwise
|
|
static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
|
|
InternalInstruction &insn, const MCDisassembler *Dis) {
|
|
switch (operand.type) {
|
|
default:
|
|
debug("Unexpected type for a R/M operand");
|
|
return true;
|
|
case TYPE_R8:
|
|
case TYPE_R16:
|
|
case TYPE_R32:
|
|
case TYPE_R64:
|
|
case TYPE_Rv:
|
|
case TYPE_MM:
|
|
case TYPE_MM32:
|
|
case TYPE_MM64:
|
|
case TYPE_XMM:
|
|
case TYPE_XMM32:
|
|
case TYPE_XMM64:
|
|
case TYPE_XMM128:
|
|
case TYPE_XMM256:
|
|
case TYPE_XMM512:
|
|
case TYPE_VK1:
|
|
case TYPE_VK8:
|
|
case TYPE_VK16:
|
|
case TYPE_DEBUGREG:
|
|
case TYPE_CONTROLREG:
|
|
return translateRMRegister(mcInst, insn);
|
|
case TYPE_M:
|
|
case TYPE_M8:
|
|
case TYPE_M16:
|
|
case TYPE_M32:
|
|
case TYPE_M64:
|
|
case TYPE_M128:
|
|
case TYPE_M256:
|
|
case TYPE_M512:
|
|
case TYPE_Mv:
|
|
case TYPE_M32FP:
|
|
case TYPE_M64FP:
|
|
case TYPE_M80FP:
|
|
case TYPE_M16INT:
|
|
case TYPE_M32INT:
|
|
case TYPE_M64INT:
|
|
case TYPE_M1616:
|
|
case TYPE_M1632:
|
|
case TYPE_M1664:
|
|
case TYPE_LEA:
|
|
return translateRMMemory(mcInst, insn, Dis);
|
|
}
|
|
}
|
|
|
|
/// translateFPRegister - Translates a stack position on the FPU stack to its
|
|
/// LLVM form, and appends it to an MCInst.
|
|
///
|
|
/// @param mcInst - The MCInst to append to.
|
|
/// @param stackPos - The stack position to translate.
|
|
static void translateFPRegister(MCInst &mcInst,
|
|
uint8_t stackPos) {
|
|
mcInst.addOperand(MCOperand::CreateReg(X86::ST0 + stackPos));
|
|
}
|
|
|
|
/// translateMaskRegister - Translates a 3-bit mask register number to
|
|
/// LLVM form, and appends it to an MCInst.
|
|
///
|
|
/// @param mcInst - The MCInst to append to.
|
|
/// @param maskRegNum - Number of mask register from 0 to 7.
|
|
/// @return - false on success; true otherwise.
|
|
static bool translateMaskRegister(MCInst &mcInst,
|
|
uint8_t maskRegNum) {
|
|
if (maskRegNum >= 8) {
|
|
debug("Invalid mask register number");
|
|
return true;
|
|
}
|
|
|
|
mcInst.addOperand(MCOperand::CreateReg(X86::K0 + maskRegNum));
|
|
return false;
|
|
}
|
|
|
|
/// translateOperand - Translates an operand stored in an internal instruction
|
|
/// to LLVM's format and appends it to an MCInst.
|
|
///
|
|
/// @param mcInst - The MCInst to append to.
|
|
/// @param operand - The operand, as stored in the descriptor table.
|
|
/// @param insn - The internal instruction.
|
|
/// @return - false on success; true otherwise.
|
|
static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,
|
|
InternalInstruction &insn,
|
|
const MCDisassembler *Dis) {
|
|
switch (operand.encoding) {
|
|
default:
|
|
debug("Unhandled operand encoding during translation");
|
|
return true;
|
|
case ENCODING_REG:
|
|
translateRegister(mcInst, insn.reg);
|
|
return false;
|
|
case ENCODING_WRITEMASK:
|
|
return translateMaskRegister(mcInst, insn.writemask);
|
|
case ENCODING_RM:
|
|
return translateRM(mcInst, operand, insn, Dis);
|
|
case ENCODING_CB:
|
|
case ENCODING_CW:
|
|
case ENCODING_CD:
|
|
case ENCODING_CP:
|
|
case ENCODING_CO:
|
|
case ENCODING_CT:
|
|
debug("Translation of code offsets isn't supported.");
|
|
return true;
|
|
case ENCODING_IB:
|
|
case ENCODING_IW:
|
|
case ENCODING_ID:
|
|
case ENCODING_IO:
|
|
case ENCODING_Iv:
|
|
case ENCODING_Ia:
|
|
translateImmediate(mcInst,
|
|
insn.immediates[insn.numImmediatesTranslated++],
|
|
operand,
|
|
insn,
|
|
Dis);
|
|
return false;
|
|
case ENCODING_SI:
|
|
return translateSrcIndex(mcInst, insn);
|
|
case ENCODING_DI:
|
|
return translateDstIndex(mcInst, insn);
|
|
case ENCODING_RB:
|
|
case ENCODING_RW:
|
|
case ENCODING_RD:
|
|
case ENCODING_RO:
|
|
case ENCODING_Rv:
|
|
translateRegister(mcInst, insn.opcodeRegister);
|
|
return false;
|
|
case ENCODING_FP:
|
|
translateFPRegister(mcInst, insn.modRM & 7);
|
|
return false;
|
|
case ENCODING_VVVV:
|
|
translateRegister(mcInst, insn.vvvv);
|
|
return false;
|
|
case ENCODING_DUP:
|
|
return translateOperand(mcInst, insn.operands[operand.type - TYPE_DUP0],
|
|
insn, Dis);
|
|
}
|
|
}
|
|
|
|
/// translateInstruction - Translates an internal instruction and all its
|
|
/// operands to an MCInst.
|
|
///
|
|
/// @param mcInst - The MCInst to populate with the instruction's data.
|
|
/// @param insn - The internal instruction.
|
|
/// @return - false on success; true otherwise.
|
|
static bool translateInstruction(MCInst &mcInst,
|
|
InternalInstruction &insn,
|
|
const MCDisassembler *Dis) {
|
|
if (!insn.spec) {
|
|
debug("Instruction has no specification");
|
|
return true;
|
|
}
|
|
|
|
mcInst.setOpcode(insn.instructionID);
|
|
// If when reading the prefix bytes we determined the overlapping 0xf2 or 0xf3
|
|
// prefix bytes should be disassembled as xrelease and xacquire then set the
|
|
// opcode to those instead of the rep and repne opcodes.
|
|
if (insn.xAcquireRelease) {
|
|
if(mcInst.getOpcode() == X86::REP_PREFIX)
|
|
mcInst.setOpcode(X86::XRELEASE_PREFIX);
|
|
else if(mcInst.getOpcode() == X86::REPNE_PREFIX)
|
|
mcInst.setOpcode(X86::XACQUIRE_PREFIX);
|
|
}
|
|
|
|
int index;
|
|
|
|
insn.numImmediatesTranslated = 0;
|
|
|
|
for (index = 0; index < X86_MAX_OPERANDS; ++index) {
|
|
if (insn.operands[index].encoding != ENCODING_NONE) {
|
|
if (translateOperand(mcInst, insn.operands[index], insn, Dis)) {
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
static MCDisassembler *createX86Disassembler(const Target &T,
|
|
const MCSubtargetInfo &STI) {
|
|
return new X86Disassembler::X86GenericDisassembler(STI,
|
|
T.createMCInstrInfo());
|
|
}
|
|
|
|
extern "C" void LLVMInitializeX86Disassembler() {
|
|
// Register the disassembler.
|
|
TargetRegistry::RegisterMCDisassembler(TheX86_32Target,
|
|
createX86Disassembler);
|
|
TargetRegistry::RegisterMCDisassembler(TheX86_64Target,
|
|
createX86Disassembler);
|
|
}
|