llvm-6502/test/CodeGen/MSP430/Inst8rr.ll
Chris Lattner 736a6ea3a2 Change the scheduler from adding nodes in allnodes order
to adding them in a determinstic order (bottom up from 
the root) based on the structure of the graph itself.

This updates tests for some random changes, interesting
bits: CodeGen/Blackfin/promote-logic.ll no longer crashes.
I have no idea why, but that's good right?

CodeGen/X86/2009-07-16-LoadFoldingBug.ll also fails, but
now compiles to have one fewer constant pool entry, making
the expected load that was being folded disappear.  Since it
is an unreduced mass of gnast, I just removed it.

This fixes PR6370


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97023 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-24 06:11:37 +00:00

47 lines
835 B
LLVM

; RUN: llc -march=msp430 < %s | FileCheck %s
target datalayout = "e-p:16:8:8-i8:8:8-i8:8:8-i32:8:8"
target triple = "msp430-generic-generic"
define i8 @mov(i8 %a, i8 %b) nounwind {
; CHECK: mov:
; CHECK: mov.b r14, r15
ret i8 %b
}
define i8 @add(i8 %a, i8 %b) nounwind {
; CHECK: add:
; CHECK: add.b r12, r15
%1 = add i8 %a, %b
ret i8 %1
}
define i8 @and(i8 %a, i8 %b) nounwind {
; CHECK: and:
; CHECK: and.w r14, r15
%1 = and i8 %a, %b
ret i8 %1
}
define i8 @bis(i8 %a, i8 %b) nounwind {
; CHECK: bis:
; CHECK: bis.w r14, r15
%1 = or i8 %a, %b
ret i8 %1
}
define i8 @bic(i8 %a, i8 %b) nounwind {
; CHECK: bic:
; CHECK: bic.b r14, r15
%1 = xor i8 %b, -1
%2 = and i8 %a, %1
ret i8 %2
}
define i8 @xor(i8 %a, i8 %b) nounwind {
; CHECK: xor:
; CHECK: xor.w r14, r15
%1 = xor i8 %a, %b
ret i8 %1
}