llvm-6502/test/CodeGen
Anton Korobeynikov b58d7d0312 Add stack spill / reload instructions for DTriple and DQuad register classes, which
were missed for no reason. This fixes PR13377


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161299 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-04 13:16:12 +00:00
..
ARM Add stack spill / reload instructions for DTriple and DQuad register classes, which 2012-08-04 13:16:12 +00:00
CellSPU Refactor and check "onlyReadsMemory" before optimizing builtins. 2012-08-03 23:29:17 +00:00
CPP test commit 2012-07-18 17:53:05 +00:00
Generic Fix a bug in the scalarization of BUILD_VECTOR. BUILD_VECTOR elements may be wider than the output element type. Make sure to trunc them if needed. 2012-07-15 20:39:08 +00:00
Hexagon Refactor and check "onlyReadsMemory" before optimizing builtins. 2012-08-03 23:29:17 +00:00
MBlaze
Mips 1. Redo mips16 instructions to avoid multiple opcodes for same instruction. 2012-08-03 22:57:02 +00:00
MSP430
NVPTX
PowerPC Refactor and check "onlyReadsMemory" before optimizing builtins. 2012-08-03 23:29:17 +00:00
SPARC test/CodeGen/SPARC/private.ll: Fixup. Forgot to prune old RUN lines. 2012-07-03 04:29:20 +00:00
Thumb Fix the remaining TCL-style quotes found in the testsuite. This is 2012-07-02 19:09:46 +00:00
Thumb2 [arm-fast-isel] Add support for vararg function calls. 2012-07-19 09:49:00 +00:00
X86 Refactor and check "onlyReadsMemory" before optimizing builtins. 2012-08-03 23:29:17 +00:00
XCore