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b58f498f75
a virtual register to eliminate a frame index, it can return that register and the constant stored there to PEI to track. When scavenging to allocate for those registers, PEI then tracks the last-used register and value, and if it is still available and matches the value for the next index, reuses the existing value rather and removes the re-materialization instructions. Fancier tracking and adjustment of scavenger allocations to keep more values live for longer is possible, but not yet implemented and would likely be better done via a different, less special-purpose, approach to the problem. eliminateFrameIndex() is modified so the target implementations can return the registers they wish to be tracked for reuse. ARM Thumb1 implements and utilizes the new mechanism. All other targets are simply modified to adjust for the changed eliminateFrameIndex() prototype. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83467 91177308-0d34-0410-b5e6-96231b3b80d8
75 lines
2.8 KiB
C++
75 lines
2.8 KiB
C++
//===- Thumb1RegisterInfo.h - Thumb-1 Register Information Impl ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Thumb-1 implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef THUMB1REGISTERINFO_H
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#define THUMB1REGISTERINFO_H
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#include "ARM.h"
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#include "ARMRegisterInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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namespace llvm {
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class ARMSubtarget;
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class ARMBaseInstrInfo;
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class Type;
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struct Thumb1RegisterInfo : public ARMBaseRegisterInfo {
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public:
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Thumb1RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
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/// emitLoadConstPool - Emits a load from constpool to materialize the
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/// specified immediate.
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void emitLoadConstPool(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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DebugLoc dl,
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unsigned DestReg, unsigned SubIdx, int Val,
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ARMCC::CondCodes Pred = ARMCC::AL,
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unsigned PredReg = 0) const;
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/// Code Generation virtual methods...
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const TargetRegisterClass *
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getPhysicalRegisterRegClass(unsigned Reg, EVT VT = MVT::Other) const;
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bool requiresRegisterScavenging(const MachineFunction &MF) const;
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bool hasReservedCallFrame(MachineFunction &MF) const;
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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// rewrite MI to access 'Offset' bytes from the FP. Return the offset that
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// could not be handled directly in MI.
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int rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
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unsigned FrameReg, int Offset,
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unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc) const;
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bool saveScavengerRegister(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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const TargetRegisterClass *RC,
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unsigned Reg) const;
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void restoreScavengerRegister(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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const TargetRegisterClass *RC,
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unsigned Reg) const;
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unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, int *Value = NULL,
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RegScavenger *RS = NULL) const;
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void emitPrologue(MachineFunction &MF) const;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
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};
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}
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#endif // THUMB1REGISTERINFO_H
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