mirror of
https://github.com/c64scene-ar/llvm-6502.git
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055ac429cc
The SystemZ port currently relies on the order of the instruction operands
matching the order of the instruction field lists. This isn't desirable
for disassembly, where the two are matched only by name. E.g. the R1 and R2
fields of an RR instruction should have corresponding R1 and R2 operands.
The main complication is that addresses are compound operands,
and as far as I know there is no mechanism to allow individual
suboperands to be selected by name in "let Inst{...} = ..." assignments.
Luckily it doesn't really matter though. The SystemZ instruction
encoding groups all address fields together in a predictable order,
so it's just as valid to see the entire compound address operand as
a single field. That's the approach taken in this patch.
Matching by name in turn means that the operands to COPY SIGN and
CONVERT TO FIXED instructions can be given in natural order.
(It was easier to do this at the same time as the rename,
since otherwise the intermediate step was too confusing.)
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181769 91177308-0d34-0410-b5e6-96231b3b80d8
950 lines
33 KiB
TableGen
950 lines
33 KiB
TableGen
//==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Basic SystemZ instruction definition
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//===----------------------------------------------------------------------===//
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class InstSystemZ<int size, dag outs, dag ins, string asmstr,
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list<dag> pattern> : Instruction {
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let Namespace = "SystemZ";
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let Size = size;
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let Pattern = pattern;
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let AsmString = asmstr;
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// Used to identify a group of related instructions, such as ST and STY.
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string Function = "";
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// "12" for an instruction that has a ...Y equivalent, "20" for that
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// ...Y equivalent.
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string PairType = "none";
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// True if this instruction is a simple D(X,B) load of a register
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// (with no sign or zero extension).
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bit SimpleBDXLoad = 0;
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// True if this instruction is a simple D(X,B) store of a register
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// (with no truncation).
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bit SimpleBDXStore = 0;
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// True if this instruction has a 20-bit displacement field.
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bit Has20BitOffset = 0;
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// True if addresses in this instruction have an index register.
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bit HasIndex = 0;
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// True if this is a 128-bit pseudo instruction that combines two 64-bit
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// operations.
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bit Is128Bit = 0;
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let TSFlags{0} = SimpleBDXLoad;
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let TSFlags{1} = SimpleBDXStore;
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let TSFlags{2} = Has20BitOffset;
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let TSFlags{3} = HasIndex;
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let TSFlags{4} = Is128Bit;
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}
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//===----------------------------------------------------------------------===//
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// Mappings between instructions
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//===----------------------------------------------------------------------===//
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// Return the version of an instruction that has an unsigned 12-bit
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// displacement.
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def getDisp12Opcode : InstrMapping {
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let FilterClass = "InstSystemZ";
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let RowFields = ["Function"];
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let ColFields = ["PairType"];
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let KeyCol = ["20"];
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let ValueCols = [["12"]];
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}
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// Return the version of an instruction that has a signed 20-bit displacement.
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def getDisp20Opcode : InstrMapping {
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let FilterClass = "InstSystemZ";
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let RowFields = ["Function"];
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let ColFields = ["PairType"];
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let KeyCol = ["12"];
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let ValueCols = [["20"]];
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}
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//===----------------------------------------------------------------------===//
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// Instruction formats
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//===----------------------------------------------------------------------===//
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//
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// Formats are specified using operand field declarations of the form:
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//
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// bits<4> Rn : register input or output for operand n
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// bits<m> In : immediate value of width m for operand n
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// bits<4> BDn : address operand n, which has a base and a displacement
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// bits<m> XBDn : address operand n, which has an index, a base and a
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// displacement
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// bits<4> Xn : index register for address operand n
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// bits<4> Mn : mode value for operand n
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//
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// The operand numbers ("n" in the list above) follow the architecture manual.
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// Assembly operands sometimes have a different order; in particular, R3 often
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// is often written between operands 1 and 2.
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//
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//===----------------------------------------------------------------------===//
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class InstRI<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<4, outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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bits<4> R1;
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bits<16> I2;
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let Inst{31-24} = op{11-4};
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let Inst{23-20} = R1;
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let Inst{19-16} = op{3-0};
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let Inst{15-0} = I2;
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}
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class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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bits<4> R1;
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bits<4> R2;
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bits<8> I3;
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bits<8> I4;
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bits<8> I5;
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let Inst{47-40} = op{15-8};
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let Inst{39-36} = R1;
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let Inst{35-32} = R2;
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let Inst{31-24} = I3;
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let Inst{23-16} = I4;
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let Inst{15-8} = I5;
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let Inst{7-0} = op{7-0};
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}
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class InstRIL<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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bits<4> R1;
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bits<32> I2;
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let Inst{47-40} = op{11-4};
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let Inst{39-36} = R1;
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let Inst{35-32} = op{3-0};
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let Inst{31-0} = I2;
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}
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class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<2, outs, ins, asmstr, pattern> {
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field bits<16> Inst;
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bits<4> R1;
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bits<4> R2;
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let Inst{15-8} = op;
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let Inst{7-4} = R1;
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let Inst{3-0} = R2;
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}
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class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<4, outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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bits<4> R1;
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bits<4> R3;
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bits<4> R2;
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let Inst{31-16} = op;
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let Inst{15-12} = R1;
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let Inst{11-8} = 0;
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let Inst{7-4} = R3;
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let Inst{3-0} = R2;
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}
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class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<4, outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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bits<4> R1;
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bits<4> R2;
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let Inst{31-16} = op;
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let Inst{15-8} = 0;
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let Inst{7-4} = R1;
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let Inst{3-0} = R2;
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}
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class InstRRF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<4, outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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bits<4> R1;
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bits<4> R2;
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bits<4> R3;
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let Inst{31-16} = op;
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let Inst{15-12} = R3;
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let Inst{11-8} = 0;
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let Inst{7-4} = R1;
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let Inst{3-0} = R2;
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}
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class InstRX<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<4, outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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bits<4> R1;
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bits<20> XBD2;
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let Inst{31-24} = op;
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let Inst{23-20} = R1;
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let Inst{19-0} = XBD2;
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let HasIndex = 1;
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}
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class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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bits<4> R1;
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bits<20> XBD2;
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let Inst{47-40} = op{15-8};
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let Inst{39-36} = R1;
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let Inst{35-16} = XBD2;
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let Inst{15-8} = 0;
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let Inst{7-0} = op{7-0};
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let HasIndex = 1;
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}
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class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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bits<4> R1;
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bits<4> R3;
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bits<20> XBD2;
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let Inst{47-40} = op{15-8};
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let Inst{39-36} = R3;
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let Inst{35-16} = XBD2;
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let Inst{15-12} = R1;
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let Inst{11-8} = 0;
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let Inst{7-0} = op{7-0};
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let HasIndex = 1;
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}
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class InstRXY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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bits<4> R1;
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bits<28> XBD2;
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let Inst{47-40} = op{15-8};
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let Inst{39-36} = R1;
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let Inst{35-8} = XBD2;
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let Inst{7-0} = op{7-0};
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let Has20BitOffset = 1;
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let HasIndex = 1;
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}
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class InstRS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<4, outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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bits<4> R1;
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bits<4> R3;
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bits<16> BD2;
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let Inst{31-24} = op;
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let Inst{23-20} = R1;
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let Inst{19-16} = R3;
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let Inst{15-0} = BD2;
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}
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class InstRSY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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bits<4> R1;
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bits<4> R3;
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bits<24> BD2;
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let Inst{47-40} = op{15-8};
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let Inst{39-36} = R1;
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let Inst{35-32} = R3;
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let Inst{31-8} = BD2;
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let Inst{7-0} = op{7-0};
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let Has20BitOffset = 1;
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}
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class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<4, outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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bits<16> BD1;
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bits<8> I2;
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let Inst{31-24} = op;
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let Inst{23-16} = I2;
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let Inst{15-0} = BD1;
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}
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class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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bits<16> BD1;
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bits<16> I2;
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let Inst{47-32} = op;
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let Inst{31-16} = BD1;
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let Inst{15-0} = I2;
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}
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class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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bits<24> BD1;
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bits<8> I2;
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let Inst{47-40} = op{15-8};
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let Inst{39-32} = I2;
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let Inst{31-8} = BD1;
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let Inst{7-0} = op{7-0};
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let Has20BitOffset = 1;
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}
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//===----------------------------------------------------------------------===//
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// Instruction definitions with semantics
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//===----------------------------------------------------------------------===//
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//
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// These classes have the form <Category><Format>, where <Format> is one
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// of the formats defined above and where <Category> describes the inputs
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// and outputs. <Category> can be one of:
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//
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// Inherent:
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// One register output operand and no input operands.
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//
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// Store:
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// One register or immediate input operand and one address input operand.
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// The instruction stores the first operand to the address.
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//
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// This category is used for both pure and truncating stores.
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//
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// LoadMultiple:
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// One address input operand and two explicit output operands.
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// The instruction loads a range of registers from the address,
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// with the explicit operands giving the first and last register
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// to load. Other loaded registers are added as implicit definitions.
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//
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// StoreMultiple:
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// Two explicit input register operands and an address operand.
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// The instruction stores a range of registers to the address,
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// with the explicit operands giving the first and last register
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// to store. Other stored registers are added as implicit uses.
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//
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// Unary:
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// One register output operand and one input operand. The input
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// operand may be a register, immediate or memory.
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//
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// Binary:
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// One register output operand and two input operands. The first
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// input operand is always a register and he second may be a register,
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// immediate or memory.
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//
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// Shift:
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// One register output operand and two input operands. The first
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// input operand is a register and the second has the same form as
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// an address (although it isn't actually used to address memory).
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//
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// Compare:
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// Two input operands. The first operand is always a register,
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// the second may be a register, immediate or memory.
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//
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// Ternary:
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// One register output operand and three register input operands.
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//
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// CmpSwap:
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// One output operand and three input operands. The first two
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// operands are registers and the third is an address. The instruction
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// both reads from and writes to the address.
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//
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// RotateSelect:
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// One output operand and five input operands. The first two operands
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// are registers and the other three are immediates.
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//
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// The format determines which input operands are tied to output operands,
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// and also determines the shape of any address operand.
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//
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// Multiclasses of the form <Category><Format>Pair define two instructions,
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// one with <Category><Format> and one with <Category><Format>Y. The name
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// of the first instruction has no suffix, the name of the second has
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// an extra "y".
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//
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//===----------------------------------------------------------------------===//
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class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
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dag src>
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: InstRRE<opcode, (outs cls:$R1), (ins),
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mnemonic#"\t$R1",
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[(set cls:$R1, src)]> {
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let R2 = 0;
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}
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class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
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: InstRSY<opcode, (outs cls:$R1, cls:$R3), (ins bdaddr20only:$BD2),
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mnemonic#"\t$R1, $R3, $BD2", []> {
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let mayLoad = 1;
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}
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class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
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RegisterOperand cls>
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: InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2),
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mnemonic#"\t$R1, $I2",
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[(operator cls:$R1, pcrel32:$I2)]> {
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let mayStore = 1;
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// We want PC-relative addresses to be tried ahead of BD and BDX addresses.
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// However, BDXs have two extra operands and are therefore 6 units more
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// complex.
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let AddedComplexity = 7;
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}
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class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
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RegisterOperand cls, AddressingMode mode = bdxaddr12only>
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: InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2),
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mnemonic#"\t$R1, $XBD2",
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[(operator cls:$R1, mode:$XBD2)]> {
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let mayStore = 1;
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}
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class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
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RegisterOperand cls, AddressingMode mode = bdxaddr20only>
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: InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2),
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mnemonic#"\t$R1, $XBD2",
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[(operator cls:$R1, mode:$XBD2)]> {
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let mayStore = 1;
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}
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multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
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SDPatternOperator operator, RegisterOperand cls> {
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let Function = mnemonic ## #cls in {
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let PairType = "12" in
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def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bdxaddr12pair>;
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let PairType = "20" in
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def Y : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bdxaddr20pair>;
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}
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}
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class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
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: InstRSY<opcode, (outs), (ins cls:$R1, cls:$R3, bdaddr20only:$BD2),
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mnemonic#"\t$R1, $R3, $BD2", []> {
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let mayStore = 1;
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}
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class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
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Immediate imm, AddressingMode mode = bdaddr12only>
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: InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
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mnemonic#"\t$BD1, $I2",
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[(operator imm:$I2, mode:$BD1)]> {
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let mayStore = 1;
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}
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class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
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Immediate imm, AddressingMode mode = bdaddr20only>
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: InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
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mnemonic#"\t$BD1, $I2",
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[(operator imm:$I2, mode:$BD1)]> {
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let mayStore = 1;
|
|
}
|
|
|
|
class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
Immediate imm>
|
|
: InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
|
|
mnemonic#"\t$BD1, $I2",
|
|
[(operator imm:$I2, bdaddr12only:$BD1)]> {
|
|
let mayStore = 1;
|
|
}
|
|
|
|
multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
|
|
SDPatternOperator operator, Immediate imm> {
|
|
let Function = mnemonic in {
|
|
let PairType = "12" in
|
|
def "" : StoreSI<mnemonic, siOpcode, operator, imm, bdaddr12pair>;
|
|
let PairType = "20" in
|
|
def Y : StoreSIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
|
|
}
|
|
}
|
|
|
|
class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
|
: InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2),
|
|
mnemonic#"\t$R1, $R2",
|
|
[(set cls1:$R1, (operator cls2:$R2))]>;
|
|
|
|
class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
|
: InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2),
|
|
mnemonic#"\t$R1, $R2",
|
|
[(set cls1:$R1, (operator cls2:$R2))]>;
|
|
|
|
class UnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
|
|
RegisterOperand cls2>
|
|
: InstRRF<opcode, (outs cls1:$R1), (ins uimm8zx4:$R3, cls2:$R2),
|
|
mnemonic#"\t$R1, $R3, $R2", []>;
|
|
|
|
class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, Immediate imm>
|
|
: InstRI<opcode, (outs cls:$R1), (ins imm:$I2),
|
|
mnemonic#"\t$R1, $I2",
|
|
[(set cls:$R1, (operator imm:$I2))]>;
|
|
|
|
class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, Immediate imm>
|
|
: InstRIL<opcode, (outs cls:$R1), (ins imm:$I2),
|
|
mnemonic#"\t$R1, $I2",
|
|
[(set cls:$R1, (operator imm:$I2))]>;
|
|
|
|
class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls>
|
|
: InstRIL<opcode, (outs cls:$R1), (ins pcrel32:$I2),
|
|
mnemonic#"\t$R1, $I2",
|
|
[(set cls:$R1, (operator pcrel32:$I2))]> {
|
|
let mayLoad = 1;
|
|
// We want PC-relative addresses to be tried ahead of BD and BDX addresses.
|
|
// However, BDXs have two extra operands and are therefore 6 units more
|
|
// complex.
|
|
let AddedComplexity = 7;
|
|
}
|
|
|
|
class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, AddressingMode mode = bdxaddr12only>
|
|
: InstRX<opcode, (outs cls:$R1), (ins mode:$XBD2),
|
|
mnemonic#"\t$R1, $XBD2",
|
|
[(set cls:$R1, (operator mode:$XBD2))]> {
|
|
let mayLoad = 1;
|
|
}
|
|
|
|
class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls>
|
|
: InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2),
|
|
mnemonic#"\t$R1, $XBD2",
|
|
[(set cls:$R1, (operator bdxaddr12only:$XBD2))]> {
|
|
let mayLoad = 1;
|
|
}
|
|
|
|
class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, AddressingMode mode = bdxaddr20only>
|
|
: InstRXY<opcode, (outs cls:$R1), (ins mode:$XBD2),
|
|
mnemonic#"\t$R1, $XBD2",
|
|
[(set cls:$R1, (operator mode:$XBD2))]> {
|
|
let mayLoad = 1;
|
|
}
|
|
|
|
multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
|
|
SDPatternOperator operator, RegisterOperand cls> {
|
|
let Function = mnemonic ## #cls in {
|
|
let PairType = "12" in
|
|
def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bdxaddr12pair>;
|
|
let PairType = "20" in
|
|
def Y : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bdxaddr20pair>;
|
|
}
|
|
}
|
|
|
|
class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
|
: InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
|
|
mnemonic#"\t$R1, $R2",
|
|
[(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
}
|
|
|
|
class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
|
: InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
|
|
mnemonic#"\t$R1, $R2",
|
|
[(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
}
|
|
|
|
class BinaryRRF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
|
: InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R3, cls2:$R2),
|
|
mnemonic#"\t$R1, $R3, $R2",
|
|
[(set cls1:$R1, (operator cls1:$R3, cls2:$R2))]>;
|
|
|
|
class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, Immediate imm>
|
|
: InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
|
|
mnemonic#"\t$R1, $I2",
|
|
[(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
}
|
|
|
|
class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, Immediate imm>
|
|
: InstRIL<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
|
|
mnemonic#"\t$R1, $I2",
|
|
[(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
}
|
|
|
|
class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, SDPatternOperator load,
|
|
AddressingMode mode = bdxaddr12only>
|
|
: InstRX<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
|
|
mnemonic#"\t$R1, $XBD2",
|
|
[(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
let mayLoad = 1;
|
|
}
|
|
|
|
class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, SDPatternOperator load>
|
|
: InstRXE<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
|
|
mnemonic#"\t$R1, $XBD2",
|
|
[(set cls:$R1, (operator cls:$R1src,
|
|
(load bdxaddr12only:$XBD2)))]> {
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
let mayLoad = 1;
|
|
}
|
|
|
|
class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, SDPatternOperator load,
|
|
AddressingMode mode = bdxaddr20only>
|
|
: InstRXY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
|
|
mnemonic#"\t$R1, $XBD2",
|
|
[(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
let mayLoad = 1;
|
|
}
|
|
|
|
multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
|
|
SDPatternOperator operator, RegisterOperand cls,
|
|
SDPatternOperator load> {
|
|
let Function = mnemonic ## #cls in {
|
|
let PairType = "12" in
|
|
def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bdxaddr12pair>;
|
|
let PairType = "20" in
|
|
def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load,
|
|
bdxaddr20pair>;
|
|
}
|
|
}
|
|
|
|
class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
Operand imm, AddressingMode mode = bdaddr12only>
|
|
: InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
|
|
mnemonic#"\t$BD1, $I2",
|
|
[(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
|
|
let mayLoad = 1;
|
|
let mayStore = 1;
|
|
}
|
|
|
|
class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
Operand imm, AddressingMode mode = bdaddr20only>
|
|
: InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
|
|
mnemonic#"\t$BD1, $I2",
|
|
[(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
|
|
let mayLoad = 1;
|
|
let mayStore = 1;
|
|
}
|
|
|
|
multiclass BinarySIPair<string mnemonic, bits<8> siOpcode,
|
|
bits<16> siyOpcode, SDPatternOperator operator,
|
|
Operand imm> {
|
|
let Function = mnemonic ## #cls in {
|
|
let PairType = "12" in
|
|
def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>;
|
|
let PairType = "20" in
|
|
def Y : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
|
|
}
|
|
}
|
|
|
|
class ShiftRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, AddressingMode mode>
|
|
: InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2),
|
|
mnemonic#"\t$R1, $BD2",
|
|
[(set cls:$R1, (operator cls:$R1src, mode:$BD2))]> {
|
|
let R3 = 0;
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
}
|
|
|
|
class ShiftRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, AddressingMode mode>
|
|
: InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
|
|
mnemonic#"\t$R1, $R3, $BD2",
|
|
[(set cls:$R1, (operator cls:$R3, mode:$BD2))]>;
|
|
|
|
class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
|
: InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2),
|
|
mnemonic#"\t$R1, $R2",
|
|
[(operator cls1:$R1, cls2:$R2)]>;
|
|
|
|
class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
|
: InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
|
|
mnemonic#"\t$R1, $R2",
|
|
[(operator cls1:$R1, cls2:$R2)]>;
|
|
|
|
class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, Immediate imm>
|
|
: InstRI<opcode, (outs), (ins cls:$R1, imm:$I2),
|
|
mnemonic#"\t$R1, $I2",
|
|
[(operator cls:$R1, imm:$I2)]>;
|
|
|
|
class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, Immediate imm>
|
|
: InstRIL<opcode, (outs), (ins cls:$R1, imm:$I2),
|
|
mnemonic#"\t$R1, $I2",
|
|
[(operator cls:$R1, imm:$I2)]>;
|
|
|
|
class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, SDPatternOperator load>
|
|
: InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2),
|
|
mnemonic#"\t$R1, $I2",
|
|
[(operator cls:$R1, (load pcrel32:$I2))]> {
|
|
let mayLoad = 1;
|
|
// We want PC-relative addresses to be tried ahead of BD and BDX addresses.
|
|
// However, BDXs have two extra operands and are therefore 6 units more
|
|
// complex.
|
|
let AddedComplexity = 7;
|
|
}
|
|
|
|
class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, SDPatternOperator load,
|
|
AddressingMode mode = bdxaddr12only>
|
|
: InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2),
|
|
mnemonic#"\t$R1, $XBD2",
|
|
[(operator cls:$R1, (load mode:$XBD2))]> {
|
|
let mayLoad = 1;
|
|
}
|
|
|
|
class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, SDPatternOperator load>
|
|
: InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
|
|
mnemonic#"\t$R1, $XBD2",
|
|
[(operator cls:$R1, (load bdxaddr12only:$XBD2))]> {
|
|
let mayLoad = 1;
|
|
}
|
|
|
|
class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, SDPatternOperator load,
|
|
AddressingMode mode = bdxaddr20only>
|
|
: InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2),
|
|
mnemonic#"\t$R1, $XBD2",
|
|
[(operator cls:$R1, (load mode:$XBD2))]> {
|
|
let mayLoad = 1;
|
|
}
|
|
|
|
multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
|
|
SDPatternOperator operator, RegisterOperand cls,
|
|
SDPatternOperator load> {
|
|
let Function = mnemonic ## #cls in {
|
|
let PairType = "12" in
|
|
def "" : CompareRX<mnemonic, rxOpcode, operator, cls,
|
|
load, bdxaddr12pair>;
|
|
let PairType = "20" in
|
|
def Y : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls,
|
|
load, bdxaddr20pair>;
|
|
}
|
|
}
|
|
|
|
class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
SDPatternOperator load, Immediate imm,
|
|
AddressingMode mode = bdaddr12only>
|
|
: InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
|
|
mnemonic#"\t$BD1, $I2",
|
|
[(operator (load mode:$BD1), imm:$I2)]> {
|
|
let mayLoad = 1;
|
|
}
|
|
|
|
class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
SDPatternOperator load, Immediate imm>
|
|
: InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
|
|
mnemonic#"\t$BD1, $I2",
|
|
[(operator (load bdaddr12only:$BD1), imm:$I2)]> {
|
|
let mayLoad = 1;
|
|
}
|
|
|
|
class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
SDPatternOperator load, Immediate imm,
|
|
AddressingMode mode = bdaddr20only>
|
|
: InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
|
|
mnemonic#"\t$BD1, $I2",
|
|
[(operator (load mode:$BD1), imm:$I2)]> {
|
|
let mayLoad = 1;
|
|
}
|
|
|
|
multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
|
|
SDPatternOperator operator, SDPatternOperator load,
|
|
Immediate imm> {
|
|
let Function = mnemonic in {
|
|
let PairType = "12" in
|
|
def "" : CompareSI<mnemonic, siOpcode, operator, load, imm, bdaddr12pair>;
|
|
let PairType = "20" in
|
|
def Y : CompareSIY<mnemonic#"y", siyOpcode, operator, load, imm,
|
|
bdaddr20pair>;
|
|
}
|
|
}
|
|
|
|
class TernaryRRD<string mnemonic, bits<16> opcode,
|
|
SDPatternOperator operator, RegisterOperand cls>
|
|
: InstRRD<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, cls:$R2),
|
|
mnemonic#"\t$R1, $R3, $R2",
|
|
[(set cls:$R1, (operator cls:$R1src, cls:$R3, cls:$R2))]> {
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
}
|
|
|
|
class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, SDPatternOperator load>
|
|
: InstRXF<opcode, (outs cls:$R1),
|
|
(ins cls:$R1src, cls:$R3, bdxaddr12only:$XBD2),
|
|
mnemonic#"\t$R1, $R3, $XBD2",
|
|
[(set cls:$R1, (operator cls:$R1src, cls:$R3,
|
|
(load bdxaddr12only:$XBD2)))]> {
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
let mayLoad = 1;
|
|
}
|
|
|
|
class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, AddressingMode mode = bdaddr12only>
|
|
: InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
|
|
mnemonic#"\t$R1, $R3, $BD2",
|
|
[(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
let mayLoad = 1;
|
|
let mayStore = 1;
|
|
}
|
|
|
|
class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, AddressingMode mode = bdaddr20only>
|
|
: InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
|
|
mnemonic#"\t$R1, $R3, $BD2",
|
|
[(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
let mayLoad = 1;
|
|
let mayStore = 1;
|
|
}
|
|
|
|
multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
|
|
SDPatternOperator operator, RegisterOperand cls> {
|
|
let Function = mnemonic ## #cls in {
|
|
let PairType = "12" in
|
|
def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>;
|
|
let PairType = "20" in
|
|
def Y : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>;
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|
}
|
|
}
|
|
|
|
class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
|
|
RegisterOperand cls2>
|
|
: InstRIEf<opcode, (outs cls1:$R1),
|
|
(ins cls1:$R1src, cls2:$R2,
|
|
uimm8zx6:$I3, uimm8zx6:$I4, uimm8zx6:$I5),
|
|
mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> {
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Pseudo instructions
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// Convenience instructions that get lowered to real instructions
|
|
// by either SystemZTargetLowering::EmitInstrWithCustomInserter()
|
|
// or SystemZInstrInfo::expandPostRAPseudo().
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class Pseudo<dag outs, dag ins, list<dag> pattern>
|
|
: InstSystemZ<0, outs, ins, "", pattern> {
|
|
let isPseudo = 1;
|
|
let isCodeGenOnly = 1;
|
|
}
|
|
|
|
// Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is
|
|
// the value of the PSW's 2-bit condition code field.
|
|
class SelectWrapper<RegisterOperand cls>
|
|
: Pseudo<(outs cls:$dst), (ins cls:$src1, cls:$src2, i8imm:$cc),
|
|
[(set cls:$dst, (z_select_ccmask cls:$src1, cls:$src2, imm:$cc))]> {
|
|
let usesCustomInserter = 1;
|
|
// Although the instructions used by these nodes do not in themselves
|
|
// change the PSW, the insertion requires new blocks, and the PSW cannot
|
|
// be live across them.
|
|
let Defs = [PSW];
|
|
let Uses = [PSW];
|
|
}
|
|
|
|
// OPERATOR is ATOMIC_SWAP or an ATOMIC_LOAD_* operation. PAT and OPERAND
|
|
// describe the second (non-memory) operand.
|
|
class AtomicLoadBinary<SDPatternOperator operator, RegisterOperand cls,
|
|
dag pat, DAGOperand operand>
|
|
: Pseudo<(outs cls:$dst), (ins bdaddr20only:$ptr, operand:$src2),
|
|
[(set cls:$dst, (operator bdaddr20only:$ptr, pat))]> {
|
|
let Defs = [PSW];
|
|
let Has20BitOffset = 1;
|
|
let mayLoad = 1;
|
|
let mayStore = 1;
|
|
let usesCustomInserter = 1;
|
|
}
|
|
|
|
// Specializations of AtomicLoadWBinary.
|
|
class AtomicLoadBinaryReg32<SDPatternOperator operator>
|
|
: AtomicLoadBinary<operator, GR32, (i32 GR32:$src2), GR32>;
|
|
class AtomicLoadBinaryImm32<SDPatternOperator operator, Immediate imm>
|
|
: AtomicLoadBinary<operator, GR32, (i32 imm:$src2), imm>;
|
|
class AtomicLoadBinaryReg64<SDPatternOperator operator>
|
|
: AtomicLoadBinary<operator, GR64, (i64 GR64:$src2), GR64>;
|
|
class AtomicLoadBinaryImm64<SDPatternOperator operator, Immediate imm>
|
|
: AtomicLoadBinary<operator, GR64, (i64 imm:$src2), imm>;
|
|
|
|
// OPERATOR is ATOMIC_SWAPW or an ATOMIC_LOADW_* operation. PAT and OPERAND
|
|
// describe the second (non-memory) operand.
|
|
class AtomicLoadWBinary<SDPatternOperator operator, dag pat,
|
|
DAGOperand operand>
|
|
: Pseudo<(outs GR32:$dst),
|
|
(ins bdaddr20only:$ptr, operand:$src2, ADDR32:$bitshift,
|
|
ADDR32:$negbitshift, uimm32:$bitsize),
|
|
[(set GR32:$dst, (operator bdaddr20only:$ptr, pat, ADDR32:$bitshift,
|
|
ADDR32:$negbitshift, uimm32:$bitsize))]> {
|
|
let Defs = [PSW];
|
|
let Has20BitOffset = 1;
|
|
let mayLoad = 1;
|
|
let mayStore = 1;
|
|
let usesCustomInserter = 1;
|
|
}
|
|
|
|
// Specializations of AtomicLoadWBinary.
|
|
class AtomicLoadWBinaryReg<SDPatternOperator operator>
|
|
: AtomicLoadWBinary<operator, (i32 GR32:$src2), GR32>;
|
|
class AtomicLoadWBinaryImm<SDPatternOperator operator, Immediate imm>
|
|
: AtomicLoadWBinary<operator, (i32 imm:$src2), imm>;
|