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58421d7d08
fixes test/Regression/CodeGen/ARM/ret_arg5.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28854 91177308-0d34-0410-b5e6-96231b3b80d8
63 lines
2.2 KiB
TableGen
63 lines
2.2 KiB
TableGen
//===- ARMRegisterInfo.td - ARM Register defs ----------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the "Instituto Nokia de Tecnologia" and
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// is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the ARM register file
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//===----------------------------------------------------------------------===//
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// Registers are identified with 4-bit ID numbers.
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class ARMReg<bits<4> num, string n> : Register<n> {
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field bits<4> Num;
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let Namespace = "ARM";
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}
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// Integer registers
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def R0 : ARMReg< 0, "R0">, DwarfRegNum<0>;
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def R1 : ARMReg< 1, "R1">, DwarfRegNum<1>;
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def R2 : ARMReg< 2, "R2">, DwarfRegNum<2>;
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def R3 : ARMReg< 3, "R3">, DwarfRegNum<3>;
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def R4 : ARMReg< 4, "R4">, DwarfRegNum<4>;
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def R5 : ARMReg< 5, "R5">, DwarfRegNum<5>;
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def R6 : ARMReg< 6, "R6">, DwarfRegNum<6>;
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def R7 : ARMReg< 7, "R7">, DwarfRegNum<7>;
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def R8 : ARMReg< 8, "R8">, DwarfRegNum<8>;
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def R9 : ARMReg< 9, "R9">, DwarfRegNum<9>;
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def R10 : ARMReg<10, "R10">, DwarfRegNum<10>;
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def R11 : ARMReg<11, "R11">, DwarfRegNum<11>;
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def R12 : ARMReg<12, "R12">, DwarfRegNum<12>;
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def R13 : ARMReg<13, "R13">, DwarfRegNum<13>;
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def R14 : ARMReg<14, "R14">, DwarfRegNum<14>;
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def R15 : ARMReg<15, "R15">, DwarfRegNum<15>;
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// Register classes.
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//
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// FIXME: the register order should be defined in terms of the preferred
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// allocation order...
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//
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def IntRegs : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
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R7, R8, R9, R10, R11, R12,
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R13, R14, R15]> {
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let MethodProtos = [{
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iterator allocation_order_end(MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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IntRegsClass::iterator
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IntRegsClass::allocation_order_end(MachineFunction &MF) const {
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// r15 == Program Counter
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// r14 == Link Register
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// r13 == Stack Pointer
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// r12 == ip (scratch)
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// r11 == Frame Pointer
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// r10 == Stack Limit
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return end() - 4;
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}
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}];
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}
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