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https://github.com/c64scene-ar/llvm-6502.git
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97de913821
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36626 91177308-0d34-0410-b5e6-96231b3b80d8
388 lines
14 KiB
C++
388 lines
14 KiB
C++
//===- IA64RegisterInfo.cpp - IA64 Register Information ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Duraid Madina and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the IA64 implementation of the MRegisterInfo class. This
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// file is responsible for the frame pointer elimination optimization on IA64.
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//
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//===----------------------------------------------------------------------===//
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#include "IA64.h"
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#include "IA64RegisterInfo.h"
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#include "IA64InstrBuilder.h"
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#include "IA64MachineFunctionInfo.h"
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#include "llvm/Constants.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineLocation.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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using namespace llvm;
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IA64RegisterInfo::IA64RegisterInfo(const TargetInstrInfo &tii)
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: IA64GenRegisterInfo(IA64::ADJUSTCALLSTACKDOWN, IA64::ADJUSTCALLSTACKUP),
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TII(tii) {}
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void IA64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, int FrameIdx,
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const TargetRegisterClass *RC) const{
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if (RC == IA64::FPRegisterClass) {
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BuildMI(MBB, MI, TII.get(IA64::STF_SPILL)).addFrameIndex(FrameIdx)
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.addReg(SrcReg, false, false, true);
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} else if (RC == IA64::GRRegisterClass) {
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BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx)
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.addReg(SrcReg, false, false, true);
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} else if (RC == IA64::PRRegisterClass) {
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/* we use IA64::r2 as a temporary register for doing this hackery. */
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// first we load 0:
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BuildMI(MBB, MI, TII.get(IA64::MOV), IA64::r2).addReg(IA64::r0);
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// then conditionally add 1:
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BuildMI(MBB, MI, TII.get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2)
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.addImm(1).addReg(SrcReg, false, false, true);
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// and then store it to the stack
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BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(IA64::r2);
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} else assert(0 &&
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"sorry, I don't know how to store this sort of reg in the stack\n");
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}
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void IA64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC)const{
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if (RC == IA64::FPRegisterClass) {
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BuildMI(MBB, MI, TII.get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx);
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} else if (RC == IA64::GRRegisterClass) {
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BuildMI(MBB, MI, TII.get(IA64::LD8), DestReg).addFrameIndex(FrameIdx);
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} else if (RC == IA64::PRRegisterClass) {
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// first we load a byte from the stack into r2, our 'predicate hackery'
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// scratch reg
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BuildMI(MBB, MI, TII.get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx);
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// then we compare it to zero. If it _is_ zero, compare-not-equal to
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// r0 gives us 0, which is what we want, so that's nice.
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BuildMI(MBB, MI, TII.get(IA64::CMPNE), DestReg).addReg(IA64::r2).addReg(IA64::r0);
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} else assert(0 &&
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"sorry, I don't know how to load this sort of reg from the stack\n");
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}
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void IA64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const {
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if(RC == IA64::PRRegisterClass ) // if a bool, we use pseudocode
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// (SrcReg) DestReg = cmp.eq.unc(r0, r0)
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BuildMI(MBB, MI, TII.get(IA64::PCMPEQUNC), DestReg)
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.addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
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else // otherwise, MOV works (for both gen. regs and FP regs)
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BuildMI(MBB, MI, TII.get(IA64::MOV), DestReg).addReg(SrcReg);
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}
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void IA64RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg,
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const MachineInstr *Orig) const {
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MachineInstr *MI = Orig->clone();
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MI->getOperand(0).setReg(DestReg);
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MBB.insert(I, MI);
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}
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const unsigned* IA64RegisterInfo::getCalleeSavedRegs() const {
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static const unsigned CalleeSavedRegs[] = {
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IA64::r5, 0
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};
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return CalleeSavedRegs;
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}
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const TargetRegisterClass* const*
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IA64RegisterInfo::getCalleeSavedRegClasses() const {
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static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
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&IA64::GRRegClass, 0
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};
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return CalleeSavedRegClasses;
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}
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BitVector IA64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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Reserved.set(IA64::r0);
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Reserved.set(IA64::r1);
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Reserved.set(IA64::r2);
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Reserved.set(IA64::r5);
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Reserved.set(IA64::r12);
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Reserved.set(IA64::r13);
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Reserved.set(IA64::r22);
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Reserved.set(IA64::rp);
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return Reserved;
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}
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//===----------------------------------------------------------------------===//
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// Stack Frame Processing methods
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//===----------------------------------------------------------------------===//
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// hasFP - Return true if the specified function should have a dedicated frame
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// pointer register. This is true if the function has variable sized allocas or
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// if frame pointer elimination is disabled.
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//
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bool IA64RegisterInfo::hasFP(const MachineFunction &MF) const {
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return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
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}
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void IA64RegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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if (hasFP(MF)) {
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// If we have a frame pointer, turn the adjcallstackup instruction into a
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// 'sub SP, <amt>' and the adjcallstackdown instruction into 'add SP,
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// <amt>'
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MachineInstr *Old = I;
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unsigned Amount = Old->getOperand(0).getImmedValue();
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if (Amount != 0) {
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// We need to keep the stack aligned properly. To do this, we round the
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// amount of space needed for the outgoing arguments up to the next
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// alignment boundary.
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unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
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Amount = (Amount+Align-1)/Align*Align;
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MachineInstr *New;
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if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) {
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New=BuildMI(TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
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.addImm(-Amount);
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} else {
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assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP);
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New=BuildMI(TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
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.addImm(Amount);
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}
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// Replace the pseudo instruction with a new instruction...
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MBB.insert(I, New);
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}
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}
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MBB.erase(I);
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}
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void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, RegScavenger *RS)const{
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assert(SPAdj == 0 && "Unexpected");
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unsigned i = 0;
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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bool FP = hasFP(MF);
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while (!MI.getOperand(i).isFrameIndex()) {
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++i;
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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int FrameIndex = MI.getOperand(i).getFrameIndex();
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// choose a base register: ( hasFP? framepointer : stack pointer )
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unsigned BaseRegister = FP ? IA64::r5 : IA64::r12;
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// Add the base register
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MI.getOperand(i).ChangeToRegister(BaseRegister, false);
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// Now add the frame object offset to the offset from r1.
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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// If we're not using a Frame Pointer that has been set to the value of the
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// SP before having the stack size subtracted from it, then add the stack size
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// to Offset to get the correct offset.
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Offset += MF.getFrameInfo()->getStackSize();
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// XXX: we use 'r22' as another hack+slash temporary register here :(
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if (Offset <= 8191 && Offset >= -8192) { // smallish offset
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// Fix up the old:
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MI.getOperand(i).ChangeToRegister(IA64::r22, false);
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//insert the new
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MachineInstr* nMI=BuildMI(TII.get(IA64::ADDIMM22), IA64::r22)
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.addReg(BaseRegister).addImm(Offset);
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MBB.insert(II, nMI);
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} else { // it's big
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//fix up the old:
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MI.getOperand(i).ChangeToRegister(IA64::r22, false);
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MachineInstr* nMI;
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nMI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(Offset);
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MBB.insert(II, nMI);
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nMI=BuildMI(TII.get(IA64::ADD), IA64::r22).addReg(BaseRegister)
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.addReg(IA64::r22);
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MBB.insert(II, nMI);
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}
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}
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void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
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MachineBasicBlock::iterator MBBI = MBB.begin();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineInstr *MI;
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bool FP = hasFP(MF);
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// first, we handle the 'alloc' instruction, that should be right up the
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// top of any function
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static const unsigned RegsInOrder[96] = { // there are 96 GPRs the
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// RSE worries about
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IA64::r32, IA64::r33, IA64::r34, IA64::r35,
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IA64::r36, IA64::r37, IA64::r38, IA64::r39, IA64::r40, IA64::r41,
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IA64::r42, IA64::r43, IA64::r44, IA64::r45, IA64::r46, IA64::r47,
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IA64::r48, IA64::r49, IA64::r50, IA64::r51, IA64::r52, IA64::r53,
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IA64::r54, IA64::r55, IA64::r56, IA64::r57, IA64::r58, IA64::r59,
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IA64::r60, IA64::r61, IA64::r62, IA64::r63, IA64::r64, IA64::r65,
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IA64::r66, IA64::r67, IA64::r68, IA64::r69, IA64::r70, IA64::r71,
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IA64::r72, IA64::r73, IA64::r74, IA64::r75, IA64::r76, IA64::r77,
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IA64::r78, IA64::r79, IA64::r80, IA64::r81, IA64::r82, IA64::r83,
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IA64::r84, IA64::r85, IA64::r86, IA64::r87, IA64::r88, IA64::r89,
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IA64::r90, IA64::r91, IA64::r92, IA64::r93, IA64::r94, IA64::r95,
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IA64::r96, IA64::r97, IA64::r98, IA64::r99, IA64::r100, IA64::r101,
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IA64::r102, IA64::r103, IA64::r104, IA64::r105, IA64::r106, IA64::r107,
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IA64::r108, IA64::r109, IA64::r110, IA64::r111, IA64::r112, IA64::r113,
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IA64::r114, IA64::r115, IA64::r116, IA64::r117, IA64::r118, IA64::r119,
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IA64::r120, IA64::r121, IA64::r122, IA64::r123, IA64::r124, IA64::r125,
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IA64::r126, IA64::r127 };
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unsigned numStackedGPRsUsed=0;
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for(int i=0; i<96; i++) {
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if(MF.isPhysRegUsed(RegsInOrder[i]))
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numStackedGPRsUsed=i+1; // (i+1 and not ++ - consider fn(fp, fp, int)
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}
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unsigned numOutRegsUsed=MF.getInfo<IA64FunctionInfo>()->outRegsUsed;
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// XXX FIXME : this code should be a bit more reliable (in case there _isn't_
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// a pseudo_alloc in the MBB)
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unsigned dstRegOfPseudoAlloc;
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for(MBBI = MBB.begin(); /*MBBI->getOpcode() != IA64::PSEUDO_ALLOC*/; ++MBBI) {
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assert(MBBI != MBB.end());
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if(MBBI->getOpcode() == IA64::PSEUDO_ALLOC) {
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dstRegOfPseudoAlloc=MBBI->getOperand(0).getReg();
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break;
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}
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}
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MI=BuildMI(TII.get(IA64::ALLOC)).addReg(dstRegOfPseudoAlloc).addImm(0). \
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addImm(numStackedGPRsUsed).addImm(numOutRegsUsed).addImm(0);
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MBB.insert(MBBI, MI);
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// Get the number of bytes to allocate from the FrameInfo
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unsigned NumBytes = MFI->getStackSize();
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if(FP)
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NumBytes += 8; // reserve space for the old FP
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// Do we need to allocate space on the stack?
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if (NumBytes == 0)
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return;
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// Add 16 bytes at the bottom of the stack (scratch area)
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// and round the size to a multiple of the alignment.
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unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
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unsigned Size = 16 + (FP ? 8 : 0);
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NumBytes = (NumBytes+Size+Align-1)/Align*Align;
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// Update frame info to pretend that this is part of the stack...
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MFI->setStackSize(NumBytes);
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// adjust stack pointer: r12 -= numbytes
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if (NumBytes <= 8191) {
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MI=BuildMI(TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
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addImm(-NumBytes);
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MBB.insert(MBBI, MI);
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} else { // we use r22 as a scratch register here
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MI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(-NumBytes);
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// FIXME: MOVLSI32 expects a _u_32imm
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MBB.insert(MBBI, MI); // first load the decrement into r22
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MI=BuildMI(TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
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MBB.insert(MBBI, MI); // then add (subtract) it to r12 (stack ptr)
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}
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// now if we need to, save the old FP and set the new
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if (FP) {
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MI = BuildMI(TII.get(IA64::ST8)).addReg(IA64::r12).addReg(IA64::r5);
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MBB.insert(MBBI, MI);
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// this must be the last instr in the prolog ? (XXX: why??)
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MI = BuildMI(TII.get(IA64::MOV), IA64::r5).addReg(IA64::r12);
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MBB.insert(MBBI, MI);
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}
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}
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void IA64RegisterInfo::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineBasicBlock::iterator MBBI = prior(MBB.end());
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MachineInstr *MI;
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assert(MBBI->getOpcode() == IA64::RET &&
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"Can only insert epilog into returning blocks");
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bool FP = hasFP(MF);
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// Get the number of bytes allocated from the FrameInfo...
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unsigned NumBytes = MFI->getStackSize();
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//now if we need to, restore the old FP
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if (FP)
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{
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//copy the FP into the SP (discards allocas)
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MI=BuildMI(TII.get(IA64::MOV), IA64::r12).addReg(IA64::r5);
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MBB.insert(MBBI, MI);
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//restore the FP
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MI=BuildMI(TII.get(IA64::LD8), IA64::r5).addReg(IA64::r5);
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MBB.insert(MBBI, MI);
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}
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if (NumBytes != 0)
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{
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if (NumBytes <= 8191) {
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MI=BuildMI(TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
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addImm(NumBytes);
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MBB.insert(MBBI, MI);
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} else {
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MI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(NumBytes);
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MBB.insert(MBBI, MI);
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MI=BuildMI(TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).
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addReg(IA64::r22);
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MBB.insert(MBBI, MI);
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}
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}
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}
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unsigned IA64RegisterInfo::getRARegister() const {
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assert(0 && "What is the return address register");
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return 0;
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}
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unsigned IA64RegisterInfo::getFrameRegister(MachineFunction &MF) const {
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return hasFP(MF) ? IA64::r5 : IA64::r12;
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}
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unsigned IA64RegisterInfo::getEHExceptionRegister() const {
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assert(0 && "What is the exception register");
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return 0;
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}
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unsigned IA64RegisterInfo::getEHHandlerRegister() const {
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assert(0 && "What is the exception handler register");
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return 0;
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}
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#include "IA64GenRegisterInfo.inc"
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