mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27315 91177308-0d34-0410-b5e6-96231b3b80d8
541 lines
27 KiB
TableGen
541 lines
27 KiB
TableGen
//===- PPCInstrAltivec.td - The PowerPC Altivec Extension --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Altivec extension to the PowerPC instruction set.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Altivec transformation functions and pattern fragments.
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//
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// VSPLT_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
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def VSPLT_get_imm : SDNodeXForm<build_vector, [{
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return getI32Imm(PPC::getVSPLTImmediate(N));
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}]>;
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def VSPLT_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isSplatShuffleMask(N);
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}], VSPLT_get_imm>;
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// VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
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def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
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char Val;
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PPC::isVecSplatImm(N, 1, &Val);
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return getI32Imm(Val);
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}]>;
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def vecspltisb : PatLeaf<(build_vector), [{
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return PPC::isVecSplatImm(N, 1);
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}], VSPLTISB_get_imm>;
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// VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
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def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
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char Val;
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PPC::isVecSplatImm(N, 2, &Val);
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return getI32Imm(Val);
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}]>;
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def vecspltish : PatLeaf<(build_vector), [{
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return PPC::isVecSplatImm(N, 2);
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}], VSPLTISH_get_imm>;
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// VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
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def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
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char Val;
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PPC::isVecSplatImm(N, 4, &Val);
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return getI32Imm(Val);
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}]>;
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def vecspltisw : PatLeaf<(build_vector), [{
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return PPC::isVecSplatImm(N, 4);
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}], VSPLTISW_get_imm>;
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class isVDOT { // vector dot instruction.
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list<Register> Defs = [CR6];
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bit RC = 1;
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}
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//===----------------------------------------------------------------------===//
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// Helpers for defining instructions that directly correspond to intrinsics.
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// VA1a_Int - A VAForm_1a intrinsic definition.
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class VA1a_Int<bits<6> xo, string opc, Intrinsic IntID>
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: VAForm_1a<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
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!strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP,
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[(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
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// VX1_Int - A VXForm_1 intrinsic definition.
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class VX1_Int<bits<11> xo, string asmstr, Intrinsic IntID>
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: VXForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFP,
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[(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB))]>;
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// VX2_Int - A VXForm_2 intrinsic definition.
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class VX2_Int<bits<11> xo, string asmstr, Intrinsic IntID>
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: VXForm_2<xo, (ops VRRC:$vD, VRRC:$vB), asmstr, VecFP,
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[(set VRRC:$vD, (IntID VRRC:$vB))]>;
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//===----------------------------------------------------------------------===//
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// Instruction Definitions.
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def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC",
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[(set VRRC:$rD, (v4f32 (undef)))]>;
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let isLoad = 1, PPC970_Unit = 2 in { // Loads.
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def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, memrr:$src),
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"lvebx $vD, $src", LdStGeneral,
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[(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
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def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, memrr:$src),
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"lvehx $vD, $src", LdStGeneral,
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[(set VRRC:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
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def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, memrr:$src),
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"lvewx $vD, $src", LdStGeneral,
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[(set VRRC:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
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def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
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"lvx $vD, $src", LdStGeneral,
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[(set VRRC:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
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def LVXL : XForm_1<31, 359, (ops VRRC:$vD, memrr:$src),
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"lvxl $vD, $src", LdStGeneral,
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[(set VRRC:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
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}
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def LVSL : XForm_1<31, 6, (ops VRRC:$vD, memrr:$src),
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"lvsl $vD, $src", LdStGeneral,
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[(set VRRC:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
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PPC970_Unit_LSU;
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def LVSR : XForm_1<31, 38, (ops VRRC:$vD, memrr:$src),
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"lvsl $vD, $src", LdStGeneral,
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[(set VRRC:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
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PPC970_Unit_LSU;
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let isStore = 1, noResults = 1, PPC970_Unit = 2 in { // Stores.
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def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, memrr:$dst),
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"stvebx $rS, $dst", LdStGeneral,
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[(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>;
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def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, memrr:$dst),
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"stvehx $rS, $dst", LdStGeneral,
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[(int_ppc_altivec_stvehx VRRC:$rS, xoaddr:$dst)]>;
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def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, memrr:$dst),
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"stvewx $rS, $dst", LdStGeneral,
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[(int_ppc_altivec_stvewx VRRC:$rS, xoaddr:$dst)]>;
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def STVX : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst),
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"stvx $rS, $dst", LdStGeneral,
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[(int_ppc_altivec_stvx VRRC:$rS, xoaddr:$dst)]>;
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def STVXL : XForm_8<31, 487, (ops VRRC:$rS, memrr:$dst),
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"stvxl $rS, $dst", LdStGeneral,
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[(int_ppc_altivec_stvxl VRRC:$rS, xoaddr:$dst)]>;
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}
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let PPC970_Unit = 5 in { // VALU Operations.
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// VA-Form instructions. 3-input AltiVec ops.
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def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
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"vmaddfp $vD, $vA, $vC, $vB", VecFP,
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[(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
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VRRC:$vB))]>,
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Requires<[FPContractions]>;
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def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
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"vnmsubfp $vD, $vA, $vC, $vB", VecFP,
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[(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
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VRRC:$vB)))]>,
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Requires<[FPContractions]>;
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def VMHADDSHS : VA1a_Int<32, "vmhaddshs", int_ppc_altivec_vmhaddshs>;
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def VMHRADDSHS : VA1a_Int<33, "vmhraddshs", int_ppc_altivec_vmhraddshs>;
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def VPERM : VA1a_Int<43, "vperm", int_ppc_altivec_vperm>;
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def VSEL : VA1a_Int<42, "vsel", int_ppc_altivec_vsel>;
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def VSLDOI : VAForm_2<44, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, u5imm:$SH),
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"vsldoi $vD, $vA, $vB, $SH", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vsldoi VRRC:$vA, VRRC:$vB,
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imm:$SH))]>;
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// VX-Form instructions. AltiVec arithmetic ops.
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def VADDCUW : VXForm_1<384, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vaddcuw $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vaddcuw VRRC:$vA, VRRC:$vB))]>;
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def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vaddfp $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
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def VADDUBM : VXForm_1<0, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vaddubm $vD, $vA, $vB", VecGeneral,
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[(set VRRC:$vD, (add (v16i8 VRRC:$vA), VRRC:$vB))]>;
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def VADDUHM : VXForm_1<64, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vadduhm $vD, $vA, $vB", VecGeneral,
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[(set VRRC:$vD, (add (v8i16 VRRC:$vA), VRRC:$vB))]>;
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def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vadduwm $vD, $vA, $vB", VecGeneral,
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[(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>;
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def VADDSBS : VXForm_1<768, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vaddsbs $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vaddsbs VRRC:$vA, VRRC:$vB))]>;
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def VADDSHS : VXForm_1<832, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vaddshs $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vaddshs VRRC:$vA, VRRC:$vB))]>;
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def VADDSWS : VXForm_1<896, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vaddsws $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vaddsws VRRC:$vA, VRRC:$vB))]>;
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def VADDUBS : VXForm_1<512, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vaddubs $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vaddubs VRRC:$vA, VRRC:$vB))]>;
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def VADDUHS : VXForm_1<576, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vadduhs $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vadduhs VRRC:$vA, VRRC:$vB))]>;
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def VADDUWS : VXForm_1<640, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vadduws $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vadduws VRRC:$vA, VRRC:$vB))]>;
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def VAND : VXForm_1<1028, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vand $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>;
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def VANDC : VXForm_1<1092, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vandc $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD, (and (v4i32 VRRC:$vA), (vnot VRRC:$vB)))]>;
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def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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"vcfsx $vD, $vB, $UIMM", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vcfsx VRRC:$vB, imm:$UIMM))]>;
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def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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"vcfux $vD, $vB, $UIMM", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vcfux VRRC:$vB, imm:$UIMM))]>;
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def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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"vctsxs $vD, $vB, $UIMM", VecFP,
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[]>;
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def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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"vctuxs $vD, $vB, $UIMM", VecFP,
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[]>;
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def VEXPTEFP : VXForm_2<394, (ops VRRC:$vD, VRRC:$vB),
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"vexptefp $vD, $vB", VecFP,
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[(set VRRC:$vD, (int_ppc_altivec_vexptefp VRRC:$vB))]>;
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def VLOGEFP : VXForm_2<458, (ops VRRC:$vD, VRRC:$vB),
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"vlogefp $vD, $vB", VecFP,
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[(set VRRC:$vD, (int_ppc_altivec_vlogefp VRRC:$vB))]>;
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def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vmaxfp $vD, $vA, $vB", VecFP,
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[]>;
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def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vminfp $vD, $vA, $vB", VecFP,
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[]>;
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def VMRGHH : VX1_Int<76 , "vmrghh $vD, $vA, $vB", int_ppc_altivec_vmrghh>;
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def VMRGHW : VX1_Int<140, "vmrghw $vD, $vA, $vB", int_ppc_altivec_vmrghw>;
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def VMRGLH : VX1_Int<332, "vmrglh $vD, $vA, $vB", int_ppc_altivec_vmrglh>;
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def VMRGLW : VX1_Int<396, "vmrglw $vD, $vA, $vB", int_ppc_altivec_vmrglw>;
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def VMSUMMBM : VA1a_Int<37, "vmsummbm", int_ppc_altivec_vmsummbm>;
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def VMSUMSHM : VA1a_Int<40, "vmsumshm", int_ppc_altivec_vmsumshm>;
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def VMSUMSHS : VA1a_Int<41, "vmsumshs", int_ppc_altivec_vmsumshs>;
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def VMSUMUBM : VA1a_Int<36, "vmsumubm", int_ppc_altivec_vmsumubm>;
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def VMSUMUHM : VA1a_Int<38, "vmsumuhm", int_ppc_altivec_vmsumuhm>;
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def VMSUMUHS : VA1a_Int<39, "vmsumuhs", int_ppc_altivec_vmsumuhs>;
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def VMULESB : VX1_Int<776, "vmulesb $vD, $vA, $vB", int_ppc_altivec_vmulesb>;
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def VMULESH : VX1_Int<840, "vmulesh $vD, $vA, $vB", int_ppc_altivec_vmulesh>;
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def VMULEUB : VX1_Int<520, "vmuleub $vD, $vA, $vB", int_ppc_altivec_vmuleub>;
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def VMULEUH : VX1_Int<584, "vmuleuh $vD, $vA, $vB", int_ppc_altivec_vmuleuh>;
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def VMULOSB : VX1_Int<264, "vmulosb $vD, $vA, $vB", int_ppc_altivec_vmulosb>;
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def VMULOSH : VX1_Int<328, "vmulosh $vD, $vA, $vB", int_ppc_altivec_vmulosh>;
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def VMULOUB : VX1_Int< 8, "vmuloub $vD, $vA, $vB", int_ppc_altivec_vmuloub>;
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def VMULOUH : VX1_Int< 72, "vmulouh $vD, $vA, $vB", int_ppc_altivec_vmulouh>;
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def VREFP : VX2_Int<266, "vrefp $vD, $vB", int_ppc_altivec_vrefp>;
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def VRFIM : VX2_Int<714, "vrfim $vD, $vB", int_ppc_altivec_vrfim>;
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def VRFIN : VX2_Int<522, "vrfin $vD, $vB", int_ppc_altivec_vrfin>;
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def VRFIP : VX2_Int<650, "vrfip $vD, $vB", int_ppc_altivec_vrfip>;
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def VRFIZ : VX2_Int<586, "vrfiz $vD, $vB", int_ppc_altivec_vrfiz>;
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def VRSQRTEFP : VX2_Int<330, "vrsqrtefp $vD, $vB", int_ppc_altivec_vrsqrtefp>;
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def VSUBCUW : VX1_Int<74, "vsubcuw $vD, $vA, $vB", int_ppc_altivec_vsubcuw>;
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def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsubfp $vD, $vA, $vB", VecGeneral,
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[(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
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def VSUBUBM : VXForm_1<1024, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsububm $vD, $vA, $vB", VecGeneral,
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[(set VRRC:$vD, (sub (v16i8 VRRC:$vA), VRRC:$vB))]>;
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def VSUBUHM : VXForm_1<1088, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsubuhm $vD, $vA, $vB", VecGeneral,
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[(set VRRC:$vD, (sub (v8i16 VRRC:$vA), VRRC:$vB))]>;
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def VSUBUWM : VXForm_1<1152, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsubuwm $vD, $vA, $vB", VecGeneral,
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[(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>;
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def VSUBSBS : VX1_Int<1792, "vsubsbs $vD, $vA, $vB", int_ppc_altivec_vsubsbs>;
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def VSUBSHS : VX1_Int<1856, "vsubshs $vD, $vA, $vB", int_ppc_altivec_vsubshs>;
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def VSUBSWS : VX1_Int<1920, "vsubsws $vD, $vA, $vB", int_ppc_altivec_vsubsws>;
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def VSUBUBS : VX1_Int<1536, "vsububs $vD, $vA, $vB", int_ppc_altivec_vsububs>;
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def VSUBUHS : VX1_Int<1600, "vsubuhs $vD, $vA, $vB", int_ppc_altivec_vsubuhs>;
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def VSUBUWS : VX1_Int<1664, "vsubuws $vD, $vA, $vB", int_ppc_altivec_vsubuws>;
|
|
def VSUMSWS : VX1_Int<1928, "vsumsws $vD, $vA, $vB", int_ppc_altivec_vsumsws>;
|
|
def VSUM2SWS: VX1_Int<1672, "vsum2sws $vD, $vA, $vB", int_ppc_altivec_vsum2sws>;
|
|
def VSUM4SBS: VX1_Int<1672, "vsum4sbs $vD, $vA, $vB", int_ppc_altivec_vsum4sbs>;
|
|
def VSUM4SHS: VX1_Int<1608, "vsum4shs $vD, $vA, $vB", int_ppc_altivec_vsum4shs>;
|
|
def VSUM4UBS: VX1_Int<1544, "vsum4ubs $vD, $vA, $vB", int_ppc_altivec_vsum4ubs>;
|
|
|
|
def VNOR : VXForm_1<1284, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vnor $vD, $vA, $vB", VecFP,
|
|
[(set VRRC:$vD, (vnot (or (v4i32 VRRC:$vA), VRRC:$vB)))]>;
|
|
def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vor $vD, $vA, $vB", VecFP,
|
|
[(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>;
|
|
def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vxor $vD, $vA, $vB", VecFP,
|
|
[(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>;
|
|
|
|
def VRLB : VX1_Int< 4, "vrlb $vD, $vA, $vB", int_ppc_altivec_vrlb>;
|
|
def VRLH : VX1_Int< 68, "vrlh $vD, $vA, $vB", int_ppc_altivec_vrlh>;
|
|
def VRLW : VX1_Int< 132, "vrlw $vD, $vA, $vB", int_ppc_altivec_vrlw>;
|
|
def VSLO : VX1_Int<1036, "vslo $vD, $vA, $vB", int_ppc_altivec_vslo>;
|
|
def VSLB : VX1_Int< 260, "vslb $vD, $vA, $vB", int_ppc_altivec_vslb>;
|
|
def VSLH : VX1_Int< 324, "vslh $vD, $vA, $vB", int_ppc_altivec_vslh>;
|
|
def VSLW : VX1_Int< 388, "vslw $vD, $vA, $vB", int_ppc_altivec_vslw>;
|
|
|
|
def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
|
|
"vspltb $vD, $vB, $UIMM", VecPerm,
|
|
[]>;
|
|
def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
|
|
"vsplth $vD, $vB, $UIMM", VecPerm,
|
|
[]>;
|
|
def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
|
|
"vspltw $vD, $vB, $UIMM", VecPerm,
|
|
[(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
|
|
VSPLT_shuffle_mask:$UIMM))]>;
|
|
|
|
def VSR : VX1_Int< 708, "vsr $vD, $vA, $vB" , int_ppc_altivec_vsr>;
|
|
def VSRO : VX1_Int<1100, "vsro $vD, $vA, $vB" , int_ppc_altivec_vsro>;
|
|
def VSRAB : VX1_Int< 772, "vsrab $vD, $vA, $vB", int_ppc_altivec_vsrab>;
|
|
def VSRAH : VX1_Int< 836, "vsrah $vD, $vA, $vB", int_ppc_altivec_vsrah>;
|
|
def VSRAW : VX1_Int< 900, "vsraw $vD, $vA, $vB", int_ppc_altivec_vsraw>;
|
|
def VSRB : VX1_Int< 516, "vsrb $vD, $vA, $vB" , int_ppc_altivec_vsrb>;
|
|
def VSRH : VX1_Int< 580, "vsrh $vD, $vA, $vB" , int_ppc_altivec_vsrh>;
|
|
def VSRW : VX1_Int< 644, "vsrw $vD, $vA, $vB" , int_ppc_altivec_vsrw>;
|
|
|
|
|
|
def VSPLTISB : VXForm_3<780, (ops VRRC:$vD, s5imm:$SIMM),
|
|
"vspltisb $vD, $SIMM", VecPerm,
|
|
[(set VRRC:$vD, (v4f32 vecspltisb:$SIMM))]>;
|
|
def VSPLTISH : VXForm_3<844, (ops VRRC:$vD, s5imm:$SIMM),
|
|
"vspltish $vD, $SIMM", VecPerm,
|
|
[(set VRRC:$vD, (v4f32 vecspltish:$SIMM))]>;
|
|
def VSPLTISW : VXForm_3<908, (ops VRRC:$vD, s5imm:$SIMM),
|
|
"vspltisw $vD, $SIMM", VecPerm,
|
|
[(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>;
|
|
|
|
// Vector Pack.
|
|
def VPKPX : VXForm_1<782, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vpkpx $vD, $vA, $vB", VecFP,
|
|
[(set VRRC:$vD,
|
|
(int_ppc_altivec_vpkpx VRRC:$vA, VRRC:$vB))]>;
|
|
def VPKSHSS : VXForm_1<398, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vpkshss $vD, $vA, $vB", VecFP,
|
|
[(set VRRC:$vD,
|
|
(int_ppc_altivec_vpkshss VRRC:$vA, VRRC:$vB))]>;
|
|
def VPKSHUS : VXForm_1<270, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vpkshus $vD, $vA, $vB", VecFP,
|
|
[(set VRRC:$vD,
|
|
(int_ppc_altivec_vpkshus VRRC:$vA, VRRC:$vB))]>;
|
|
def VPKSWSS : VXForm_1<462, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vpkswss $vD, $vA, $vB", VecFP,
|
|
[(set VRRC:$vD,
|
|
(int_ppc_altivec_vpkswss VRRC:$vA, VRRC:$vB))]>;
|
|
def VPKSWUS : VXForm_1<334, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vpkswus $vD, $vA, $vB", VecFP,
|
|
[(set VRRC:$vD,
|
|
(int_ppc_altivec_vpkswus VRRC:$vA, VRRC:$vB))]>;
|
|
def VPKUHUM : VXForm_1<14, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vpkuhum $vD, $vA, $vB", VecFP,
|
|
[/*TODO*/]>;
|
|
def VPKUHUS : VXForm_1<142, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vpkuhus $vD, $vA, $vB", VecFP,
|
|
[(set VRRC:$vD,
|
|
(int_ppc_altivec_vpkuhus VRRC:$vA, VRRC:$vB))]>;
|
|
def VPKUWUM : VXForm_1<78, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vpkuwum $vD, $vA, $vB", VecFP,
|
|
[/*TODO*/]>;
|
|
def VPKUWUS : VXForm_1<206, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vpkuwus $vD, $vA, $vB", VecFP,
|
|
[(set VRRC:$vD,
|
|
(int_ppc_altivec_vpkuwus VRRC:$vA, VRRC:$vB))]>;
|
|
|
|
// Vector Unpack.
|
|
def VUPKHPX : VXForm_2<846, (ops VRRC:$vD, VRRC:$vB),
|
|
"vupkhpx $vD, $vB", VecFP,
|
|
[(set VRRC:$vD, (int_ppc_altivec_vupkhpx VRRC:$vB))]>;
|
|
def VUPKHSB : VXForm_2<526, (ops VRRC:$vD, VRRC:$vB),
|
|
"vupkhsb $vD, $vB", VecFP,
|
|
[(set VRRC:$vD, (int_ppc_altivec_vupkhsb VRRC:$vB))]>;
|
|
def VUPKHSH : VXForm_2<590, (ops VRRC:$vD, VRRC:$vB),
|
|
"vupkhsh $vD, $vB", VecFP,
|
|
[(set VRRC:$vD, (int_ppc_altivec_vupkhsh VRRC:$vB))]>;
|
|
def VUPKLPX : VXForm_2<974, (ops VRRC:$vD, VRRC:$vB),
|
|
"vupklpx $vD, $vB", VecFP,
|
|
[(set VRRC:$vD, (int_ppc_altivec_vupklpx VRRC:$vB))]>;
|
|
def VUPKLSB : VXForm_2<654, (ops VRRC:$vD, VRRC:$vB),
|
|
"vupklsb $vD, $vB", VecFP,
|
|
[(set VRRC:$vD, (int_ppc_altivec_vupklsb VRRC:$vB))]>;
|
|
def VUPKLSH : VXForm_2<718, (ops VRRC:$vD, VRRC:$vB),
|
|
"vupklsh $vD, $vB", VecFP,
|
|
[(set VRRC:$vD, (int_ppc_altivec_vupklsh VRRC:$vB))]>;
|
|
|
|
|
|
// Altivec Comparisons.
|
|
|
|
class VCMP<bits<10> xo, string asmstr, ValueType Ty>
|
|
: VXRForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFPCompare,
|
|
[(set VRRC:$vD, (Ty (PPCvcmp VRRC:$vA, VRRC:$vB, xo)))]>;
|
|
class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
|
|
: VXRForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFPCompare,
|
|
[(set VRRC:$vD, (Ty (PPCvcmp_o VRRC:$vA, VRRC:$vB, xo)))]>,isVDOT;
|
|
|
|
// f32 element comparisons.0
|
|
def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>;
|
|
def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
|
|
def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
|
|
def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
|
|
def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
|
|
def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
|
|
def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
|
|
def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
|
|
|
|
// i8 element comparisons.
|
|
def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>;
|
|
def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>;
|
|
def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>;
|
|
def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
|
|
def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>;
|
|
def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
|
|
|
|
// i16 element comparisons.
|
|
def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>;
|
|
def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
|
|
def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>;
|
|
def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
|
|
def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
|
|
def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
|
|
|
|
// i32 element comparisons.
|
|
def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
|
|
def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
|
|
def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
|
|
def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
|
|
def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
|
|
def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
|
|
|
|
def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
|
|
"vxor $vD, $vD, $vD", VecFP,
|
|
[(set VRRC:$vD, (v4f32 immAllZerosV))]>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Additional Altivec Patterns
|
|
//
|
|
|
|
// Undef/Zero.
|
|
def : Pat<(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC))>;
|
|
def : Pat<(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC))>;
|
|
def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>;
|
|
def : Pat<(v16i8 immAllZerosV), (v16i8 (V_SET0))>;
|
|
def : Pat<(v8i16 immAllZerosV), (v8i16 (V_SET0))>;
|
|
def : Pat<(v4i32 immAllZerosV), (v4i32 (V_SET0))>;
|
|
|
|
// Loads.
|
|
def : Pat<(v16i8 (load xoaddr:$src)), (v16i8 (LVX xoaddr:$src))>;
|
|
def : Pat<(v8i16 (load xoaddr:$src)), (v8i16 (LVX xoaddr:$src))>;
|
|
def : Pat<(v4i32 (load xoaddr:$src)), (v4i32 (LVX xoaddr:$src))>;
|
|
def : Pat<(v4f32 (load xoaddr:$src)), (v4f32 (LVX xoaddr:$src))>;
|
|
|
|
// Stores.
|
|
def : Pat<(store (v16i8 VRRC:$rS), xoaddr:$dst),
|
|
(STVX (v16i8 VRRC:$rS), xoaddr:$dst)>;
|
|
def : Pat<(store (v8i16 VRRC:$rS), xoaddr:$dst),
|
|
(STVX (v8i16 VRRC:$rS), xoaddr:$dst)>;
|
|
def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
|
|
(STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
|
|
def : Pat<(store (v4f32 VRRC:$rS), xoaddr:$dst),
|
|
(STVX (v4f32 VRRC:$rS), xoaddr:$dst)>;
|
|
|
|
// Bit conversions.
|
|
def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
|
|
def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
|
|
def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
|
|
|
|
def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
|
|
def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
|
|
def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
|
|
|
|
def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
|
|
def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
|
|
def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
|
|
|
|
def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
|
|
def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
|
|
def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
|
|
|
|
// Immediate vector formation with vsplti*.
|
|
def : Pat<(v16i8 vecspltisb:$invec), (v16i8 (VSPLTISB vecspltisb:$invec))>;
|
|
def : Pat<(v16i8 vecspltish:$invec), (v16i8 (VSPLTISH vecspltish:$invec))>;
|
|
def : Pat<(v16i8 vecspltisw:$invec), (v16i8 (VSPLTISW vecspltisw:$invec))>;
|
|
|
|
def : Pat<(v8i16 vecspltisb:$invec), (v8i16 (VSPLTISB vecspltisb:$invec))>;
|
|
def : Pat<(v8i16 vecspltish:$invec), (v8i16 (VSPLTISH vecspltish:$invec))>;
|
|
def : Pat<(v8i16 vecspltisw:$invec), (v8i16 (VSPLTISW vecspltisw:$invec))>;
|
|
|
|
def : Pat<(v4i32 vecspltisb:$invec), (v4i32 (VSPLTISB vecspltisb:$invec))>;
|
|
def : Pat<(v4i32 vecspltish:$invec), (v4i32 (VSPLTISH vecspltish:$invec))>;
|
|
def : Pat<(v4i32 vecspltisw:$invec), (v4i32 (VSPLTISW vecspltisw:$invec))>;
|
|
|
|
// Logical Operations
|
|
def : Pat<(v16i8 (and VRRC:$A, VRRC:$B)), (v16i8 (VAND VRRC:$A, VRRC:$B))>;
|
|
def : Pat<(v8i16 (and VRRC:$A, VRRC:$B)), (v8i16 (VAND VRRC:$A, VRRC:$B))>;
|
|
def : Pat<(v16i8 (or VRRC:$A, VRRC:$B)), (v16i8 (VOR VRRC:$A, VRRC:$B))>;
|
|
def : Pat<(v8i16 (or VRRC:$A, VRRC:$B)), (v8i16 (VOR VRRC:$A, VRRC:$B))>;
|
|
def : Pat<(v16i8 (xor VRRC:$A, VRRC:$B)), (v16i8 (VXOR VRRC:$A, VRRC:$B))>;
|
|
def : Pat<(v8i16 (xor VRRC:$A, VRRC:$B)), (v8i16 (VXOR VRRC:$A, VRRC:$B))>;
|
|
def : Pat<(v16i8 (vnot (or VRRC:$A, VRRC:$B))),(v16i8 (VNOR VRRC:$A, VRRC:$B))>;
|
|
def : Pat<(v8i16 (vnot (or VRRC:$A, VRRC:$B))),(v8i16 (VNOR VRRC:$A, VRRC:$B))>;
|
|
def : Pat<(v16i8 (and VRRC:$A, (vnot VRRC:$B))),
|
|
(v16i8 (VANDC VRRC:$A, VRRC:$B))>;
|
|
def : Pat<(v8i16 (and VRRC:$A, (vnot VRRC:$B))),
|
|
(v8i16 (VANDC VRRC:$A, VRRC:$B))>;
|
|
|
|
def : Pat<(fmul VRRC:$vA, VRRC:$vB),
|
|
(VMADDFP VRRC:$vA, VRRC:$vB, (V_SET0))>;
|
|
|
|
// Fused multiply add and multiply sub for packed float. These are represented
|
|
// separately from the real instructions above, for operations that must have
|
|
// the additional precision, such as Newton-Rhapson (used by divide, sqrt)
|
|
def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
|
|
(VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
|
|
def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
|
|
(VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
|
|
|
|
def : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
|
|
(VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
|
|
def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
|
|
(VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
|
|
def : Pat<(vector_shuffle (v4i32 VRRC:$vB), (undef), VSPLT_shuffle_mask:$UIMM),
|
|
(v4i32 (VSPLTW VSPLT_shuffle_mask:$UIMM, VRRC:$vB))>;
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def : Pat<(PPCvperm (v4i32 VRRC:$vA), VRRC:$vB, VRRC:$vC),
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(v4i32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
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def : Pat<(PPCvperm (v4f32 VRRC:$vA), VRRC:$vB, VRRC:$vC),
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(v4f32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
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def : Pat<(PPCvperm (v8i16 VRRC:$vA), VRRC:$vB, VRRC:$vC),
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(v8i16 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
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def : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC),
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(v16i8 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
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