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da8ac5fd91
Instead, just create one, and make sure everything that needs it can access it. Previously most of the SelectionDAGISel subclasses all had their own TargetLowering object, which was redundant with the TargetLowering object in the TargetMachine subclasses, except on Sparc, where SparcTargetMachine didn't have a TargetLowering object. Change Sparc to work more like the other targets here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57016 91177308-0d34-0410-b5e6-96231b3b80d8
279 lines
8.0 KiB
C++
279 lines
8.0 KiB
C++
//===-- PIC16ISelDAGToDAG.cpp - A dag to dag inst selector for PIC16 ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the PIC16 target.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "pic16-isel"
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#include "PIC16.h"
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#include "PIC16ISelLowering.h"
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#include "PIC16RegisterInfo.h"
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#include "PIC16Subtarget.h"
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#include "PIC16TargetMachine.h"
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#include "llvm/GlobalValue.h"
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#include "llvm/Instructions.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Support/CFG.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetMachine.h"
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#include <queue>
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#include <set>
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// PIC16DAGToDAGISel - PIC16 specific code to select PIC16 machine
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// instructions for SelectionDAG operations.
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//===----------------------------------------------------------------------===//
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namespace {
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class VISIBILITY_HIDDEN PIC16DAGToDAGISel : public SelectionDAGISel {
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/// TM - Keep a reference to PIC16TargetMachine.
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PIC16TargetMachine &TM;
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public:
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explicit PIC16DAGToDAGISel(PIC16TargetMachine &tm) :
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SelectionDAGISel(*tm.getTargetLowering()),
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TM(tm) {}
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virtual void InstructionSelect();
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// Pass Name
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virtual const char *getPassName() const {
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return "PIC16 DAG->DAG Pattern Instruction Selection";
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}
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private:
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// Include the pieces autogenerated from the target description.
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#include "PIC16GenDAGISel.inc"
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SDNode *Select(SDValue N);
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// Select addressing mode. currently assume base + offset addr mode.
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bool SelectAM(SDValue Op, SDValue N, SDValue &Base, SDValue &Offset);
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bool SelectDirectAM(SDValue Op, SDValue N, SDValue &Base,
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SDValue &Offset);
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bool StoreInDirectAM(SDValue Op, SDValue N, SDValue &fsr);
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bool LoadFSR(SDValue Op, SDValue N, SDValue &Base, SDValue &Offset);
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bool LoadNothing(SDValue Op, SDValue N, SDValue &Base,
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SDValue &Offset);
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// getI8Imm - Return a target constant with the specified
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// value, of type i8.
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inline SDValue getI8Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i8);
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}
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#ifndef NDEBUG
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unsigned Indent;
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#endif
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};
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}
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/// InstructionSelect - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void PIC16DAGToDAGISel::InstructionSelect()
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{
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DEBUG(BB->dump());
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// Codegen the basic block.
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DOUT << "===== Instruction selection begins:\n";
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#ifndef NDEBUG
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Indent = 0;
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#endif
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// Select target instructions for the DAG.
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SelectRoot();
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DOUT << "===== Instruction selection ends:\n";
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CurDAG->RemoveDeadNodes();
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}
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bool PIC16DAGToDAGISel::
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SelectDirectAM (SDValue Op, SDValue N, SDValue &Base, SDValue &Offset)
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{
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GlobalAddressSDNode *GA;
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ConstantSDNode *GC;
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// if Address is FI, get the TargetFrameIndex.
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {
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DOUT << "--------- its frame Index\n";
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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if (N.getOpcode() == ISD::GlobalAddress) {
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GA = dyn_cast<GlobalAddressSDNode>(N);
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Offset = CurDAG->getTargetConstant((unsigned char)GA->getOffset(), MVT::i8);
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Base = CurDAG->getTargetGlobalAddress(GA->getGlobal(), MVT::i16,
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GA->getOffset());
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return true;
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}
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if (N.getOpcode() == ISD::ADD) {
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GC = dyn_cast<ConstantSDNode>(N.getOperand(1));
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Offset = CurDAG->getTargetConstant((unsigned char)GC->getZExtValue(),
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MVT::i8);
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if ((GA = dyn_cast<GlobalAddressSDNode>(N.getOperand(0)))) {
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Base = CurDAG->getTargetGlobalAddress(GA->getGlobal(), MVT::i16,
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GC->getZExtValue());
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return true;
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}
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else if (FrameIndexSDNode *FIN
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= dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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return true;
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}
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}
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return false;
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}
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// FIXME: must also account for preinc/predec/postinc/postdec.
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bool PIC16DAGToDAGISel::
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StoreInDirectAM (SDValue Op, SDValue N, SDValue &fsr)
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{
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RegisterSDNode *Reg;
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if (N.getOpcode() == ISD::LOAD) {
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LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
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if (LD) {
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fsr = LD->getBasePtr();
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}
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else if (isa<RegisterSDNode>(N.getNode())) {
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//FIXME an attempt to retrieve the register number
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//but does not work
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DOUT << "this is a register\n";
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Reg = dyn_cast<RegisterSDNode>(N.getNode());
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fsr = CurDAG->getRegister(Reg->getReg(),MVT::i16);
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}
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else {
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DOUT << "this is not a register\n";
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// FIXME must use whatever load is using
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fsr = CurDAG->getRegister(1,MVT::i16);
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}
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return true;
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}
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return false;
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}
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bool PIC16DAGToDAGISel::
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LoadFSR (SDValue Op, SDValue N, SDValue &Base, SDValue &Offset)
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{
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GlobalAddressSDNode *GA;
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if (N.getOpcode() == ISD::GlobalAddress) {
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GA = dyn_cast<GlobalAddressSDNode>(N);
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Offset = CurDAG->getTargetConstant((unsigned char)GA->getOffset(), MVT::i8);
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Base = CurDAG->getTargetGlobalAddress(GA->getGlobal(), MVT::i16,
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GA->getOffset());
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return true;
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}
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else if (N.getOpcode() == PIC16ISD::Package) {
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CurDAG->setGraphColor(Op.getNode(), "blue");
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CurDAG->viewGraph();
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}
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return false;
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}
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// LoadNothing - Don't thake this seriously, it will change.
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bool PIC16DAGToDAGISel::
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LoadNothing (SDValue Op, SDValue N, SDValue &Base, SDValue &Offset)
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{
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GlobalAddressSDNode *GA;
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if (N.getOpcode() == ISD::GlobalAddress) {
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GA = dyn_cast<GlobalAddressSDNode>(N);
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DOUT << "==========" << GA->getOffset() << "\n";
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Offset = CurDAG->getTargetConstant((unsigned char)GA->getOffset(), MVT::i8);
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Base = CurDAG->getTargetGlobalAddress(GA->getGlobal(), MVT::i16,
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GA->getOffset());
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return true;
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}
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return false;
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}
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/// Select - Select instructions not customized! Used for
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/// expanded, promoted and normal instructions.
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SDNode* PIC16DAGToDAGISel::Select(SDValue N)
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{
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SDNode *Node = N.getNode();
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unsigned Opcode = Node->getOpcode();
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// Dump information about the Node being selected
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#ifndef NDEBUG
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DOUT << std::string(Indent, ' ') << "Selecting: ";
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DEBUG(Node->dump(CurDAG));
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DOUT << "\n";
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Indent += 2;
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#endif
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// If we have a custom node, we already have selected!
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if (Node->isMachineOpcode()) {
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#ifndef NDEBUG
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DOUT << std::string(Indent-2, ' ') << "== ";
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DEBUG(Node->dump(CurDAG));
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DOUT << "\n";
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Indent -= 2;
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#endif
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return NULL;
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}
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///
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// FIXME: Instruction Selection not handled by custom or by the
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// auto-generated tablegen selection should be handled here.
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///
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switch(Opcode) {
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default: break;
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}
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// Select the default instruction.
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SDNode *ResNode = SelectCode(N);
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#ifndef NDEBUG
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DOUT << std::string(Indent-2, ' ') << "=> ";
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if (ResNode == NULL || ResNode == N.getNode())
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DEBUG(N.getNode()->dump(CurDAG));
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else
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DEBUG(ResNode->dump(CurDAG));
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DOUT << "\n";
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Indent -= 2;
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#endif
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return ResNode;
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}
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/// createPIC16ISelDag - This pass converts a legalized DAG into a
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/// PIC16-specific DAG, ready for instruction scheduling.
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FunctionPass *llvm::createPIC16ISelDag(PIC16TargetMachine &TM) {
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return new PIC16DAGToDAGISel(TM);
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}
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