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Refactoring; no functional changes intended Removed PostRAScheduler bits from subtargets (X86, ARM). Added PostRAScheduler bit to MCSchedModel class. This bit is set by a CPU's scheduling model (if it exists). Removed enablePostRAScheduler() function from TargetSubtargetInfo and subclasses. Fixed the existing enablePostMachineScheduler() method to use the MCSchedModel (was just returning false!). Added methods to TargetSubtargetInfo to allow overrides for AntiDepBreakMode, CriticalPathRCs, and OptLevel for PostRAScheduling. Added enablePostRAScheduler() function to PostRAScheduler class which queries the subtarget for the above values. Preserved existing scheduler behavior for ARM, MIPS, PPC, and X86: a. ARM overrides the CPU's postRA settings by enabling postRA for any non-Thumb or Thumb2 subtarget. b. MIPS overrides the CPU's postRA settings by enabling postRA for everything. c. PPC overrides the CPU's postRA settings by enabling postRA for everything. d. X86 is the only target that actually has postRA specified via sched model info. Differential Revision: http://reviews.llvm.org/D4217 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213101 91177308-0d34-0410-b5e6-96231b3b80d8
266 lines
10 KiB
C++
266 lines
10 KiB
C++
//===-- llvm/MC/MCSchedule.h - Scheduling -----------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the classes used to describe a subtarget's machine model
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// for scheduling and other instruction cost heuristics.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_MC_MCSCHEDULE_H
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#define LLVM_MC_MCSCHEDULE_H
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#include "llvm/Support/DataTypes.h"
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#include <cassert>
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namespace llvm {
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struct InstrItinerary;
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/// Define a kind of processor resource that will be modeled by the scheduler.
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struct MCProcResourceDesc {
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#ifndef NDEBUG
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const char *Name;
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#endif
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unsigned NumUnits; // Number of resource of this kind
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unsigned SuperIdx; // Index of the resources kind that contains this kind.
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// Number of resources that may be buffered.
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//
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// Buffered resources (BufferSize != 0) may be consumed at some indeterminate
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// cycle after dispatch. This should be used for out-of-order cpus when
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// instructions that use this resource can be buffered in a reservaton
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// station.
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//
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// Unbuffered resources (BufferSize == 0) always consume their resource some
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// fixed number of cycles after dispatch. If a resource is unbuffered, then
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// the scheduler will avoid scheduling instructions with conflicting resources
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// in the same cycle. This is for in-order cpus, or the in-order portion of
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// an out-of-order cpus.
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int BufferSize;
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bool operator==(const MCProcResourceDesc &Other) const {
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return NumUnits == Other.NumUnits && SuperIdx == Other.SuperIdx
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&& BufferSize == Other.BufferSize;
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}
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};
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/// Identify one of the processor resource kinds consumed by a particular
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/// scheduling class for the specified number of cycles.
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struct MCWriteProcResEntry {
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unsigned ProcResourceIdx;
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unsigned Cycles;
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bool operator==(const MCWriteProcResEntry &Other) const {
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return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles;
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}
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};
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/// Specify the latency in cpu cycles for a particular scheduling class and def
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/// index. -1 indicates an invalid latency. Heuristics would typically consider
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/// an instruction with invalid latency to have infinite latency. Also identify
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/// the WriteResources of this def. When the operand expands to a sequence of
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/// writes, this ID is the last write in the sequence.
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struct MCWriteLatencyEntry {
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int Cycles;
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unsigned WriteResourceID;
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bool operator==(const MCWriteLatencyEntry &Other) const {
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return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID;
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}
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};
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/// Specify the number of cycles allowed after instruction issue before a
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/// particular use operand reads its registers. This effectively reduces the
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/// write's latency. Here we allow negative cycles for corner cases where
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/// latency increases. This rule only applies when the entry's WriteResource
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/// matches the write's WriteResource.
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///
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/// MCReadAdvanceEntries are sorted first by operand index (UseIdx), then by
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/// WriteResourceIdx.
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struct MCReadAdvanceEntry {
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unsigned UseIdx;
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unsigned WriteResourceID;
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int Cycles;
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bool operator==(const MCReadAdvanceEntry &Other) const {
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return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID
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&& Cycles == Other.Cycles;
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}
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};
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/// Summarize the scheduling resources required for an instruction of a
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/// particular scheduling class.
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///
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/// Defined as an aggregate struct for creating tables with initializer lists.
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struct MCSchedClassDesc {
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static const unsigned short InvalidNumMicroOps = UINT16_MAX;
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static const unsigned short VariantNumMicroOps = UINT16_MAX - 1;
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#ifndef NDEBUG
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const char* Name;
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#endif
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unsigned short NumMicroOps;
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bool BeginGroup;
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bool EndGroup;
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unsigned WriteProcResIdx; // First index into WriteProcResTable.
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unsigned NumWriteProcResEntries;
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unsigned WriteLatencyIdx; // First index into WriteLatencyTable.
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unsigned NumWriteLatencyEntries;
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unsigned ReadAdvanceIdx; // First index into ReadAdvanceTable.
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unsigned NumReadAdvanceEntries;
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bool isValid() const {
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return NumMicroOps != InvalidNumMicroOps;
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}
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bool isVariant() const {
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return NumMicroOps == VariantNumMicroOps;
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}
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};
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/// Machine model for scheduling, bundling, and heuristics.
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///
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/// The machine model directly provides basic information about the
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/// microarchitecture to the scheduler in the form of properties. It also
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/// optionally refers to scheduler resource tables and itinerary
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/// tables. Scheduler resource tables model the latency and cost for each
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/// instruction type. Itinerary tables are an independent mechanism that
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/// provides a detailed reservation table describing each cycle of instruction
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/// execution. Subtargets may define any or all of the above categories of data
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/// depending on the type of CPU and selected scheduler.
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class MCSchedModel {
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public:
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static MCSchedModel DefaultSchedModel; // For unknown processors.
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// IssueWidth is the maximum number of instructions that may be scheduled in
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// the same per-cycle group.
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unsigned IssueWidth;
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static const unsigned DefaultIssueWidth = 1;
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// MicroOpBufferSize is the number of micro-ops that the processor may buffer
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// for out-of-order execution.
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//
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// "0" means operations that are not ready in this cycle are not considered
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// for scheduling (they go in the pending queue). Latency is paramount. This
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// may be more efficient if many instructions are pending in a schedule.
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//
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// "1" means all instructions are considered for scheduling regardless of
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// whether they are ready in this cycle. Latency still causes issue stalls,
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// but we balance those stalls against other heuristics.
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//
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// "> 1" means the processor is out-of-order. This is a machine independent
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// estimate of highly machine specific characteristics such as the register
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// renaming pool and reorder buffer.
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unsigned MicroOpBufferSize;
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static const unsigned DefaultMicroOpBufferSize = 0;
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// LoopMicroOpBufferSize is the number of micro-ops that the processor may
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// buffer for optimized loop execution. More generally, this represents the
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// optimal number of micro-ops in a loop body. A loop may be partially
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// unrolled to bring the count of micro-ops in the loop body closer to this
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// number.
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unsigned LoopMicroOpBufferSize;
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static const unsigned DefaultLoopMicroOpBufferSize = 0;
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// LoadLatency is the expected latency of load instructions.
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//
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// If MinLatency >= 0, this may be overriden for individual load opcodes by
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// InstrItinerary OperandCycles.
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unsigned LoadLatency;
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static const unsigned DefaultLoadLatency = 4;
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// HighLatency is the expected latency of "very high latency" operations.
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// See TargetInstrInfo::isHighLatencyDef().
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// By default, this is set to an arbitrarily high number of cycles
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// likely to have some impact on scheduling heuristics.
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// If MinLatency >= 0, this may be overriden by InstrItinData OperandCycles.
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unsigned HighLatency;
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static const unsigned DefaultHighLatency = 10;
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// MispredictPenalty is the typical number of extra cycles the processor
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// takes to recover from a branch misprediction.
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unsigned MispredictPenalty;
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static const unsigned DefaultMispredictPenalty = 10;
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bool PostRAScheduler; // default value is false
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bool CompleteModel;
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private:
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unsigned ProcID;
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const MCProcResourceDesc *ProcResourceTable;
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const MCSchedClassDesc *SchedClassTable;
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unsigned NumProcResourceKinds;
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unsigned NumSchedClasses;
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// Instruction itinerary tables used by InstrItineraryData.
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friend class InstrItineraryData;
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const InstrItinerary *InstrItineraries;
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public:
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// Default's must be specified as static const literals so that tablegenerated
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// target code can use it in static initializers. The defaults need to be
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// initialized in this default ctor because some clients directly instantiate
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// MCSchedModel instead of using a generated itinerary.
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MCSchedModel(): IssueWidth(DefaultIssueWidth),
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MicroOpBufferSize(DefaultMicroOpBufferSize),
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LoopMicroOpBufferSize(DefaultLoopMicroOpBufferSize),
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LoadLatency(DefaultLoadLatency),
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HighLatency(DefaultHighLatency),
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MispredictPenalty(DefaultMispredictPenalty),
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PostRAScheduler(false), CompleteModel(true),
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ProcID(0), ProcResourceTable(nullptr),
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SchedClassTable(nullptr), NumProcResourceKinds(0),
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NumSchedClasses(0), InstrItineraries(nullptr) {
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(void)NumProcResourceKinds;
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(void)NumSchedClasses;
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}
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// Table-gen driven ctor.
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MCSchedModel(unsigned iw, int mbs, int lmbs, unsigned ll, unsigned hl,
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unsigned mp, bool postRASched, bool cm, unsigned pi,
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const MCProcResourceDesc *pr, const MCSchedClassDesc *sc,
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unsigned npr, unsigned nsc, const InstrItinerary *ii):
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IssueWidth(iw), MicroOpBufferSize(mbs), LoopMicroOpBufferSize(lmbs),
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LoadLatency(ll), HighLatency(hl),
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MispredictPenalty(mp), PostRAScheduler(postRASched),
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CompleteModel(cm), ProcID(pi),
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ProcResourceTable(pr), SchedClassTable(sc), NumProcResourceKinds(npr),
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NumSchedClasses(nsc), InstrItineraries(ii) {}
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unsigned getProcessorID() const { return ProcID; }
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/// Does this machine model include instruction-level scheduling.
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bool hasInstrSchedModel() const { return SchedClassTable; }
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/// Return true if this machine model data for all instructions with a
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/// scheduling class (itinerary class or SchedRW list).
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bool isComplete() const { return CompleteModel; }
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unsigned getNumProcResourceKinds() const {
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return NumProcResourceKinds;
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}
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const MCProcResourceDesc *getProcResource(unsigned ProcResourceIdx) const {
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assert(hasInstrSchedModel() && "No scheduling machine model");
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assert(ProcResourceIdx < NumProcResourceKinds && "bad proc resource idx");
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return &ProcResourceTable[ProcResourceIdx];
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}
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const MCSchedClassDesc *getSchedClassDesc(unsigned SchedClassIdx) const {
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assert(hasInstrSchedModel() && "No scheduling machine model");
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assert(SchedClassIdx < NumSchedClasses && "bad scheduling class idx");
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return &SchedClassTable[SchedClassIdx];
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}
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};
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} // End llvm namespace
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#endif
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