mirror of
https://github.com/c64scene-ar/llvm-6502.git
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1722f061a3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89574 91177308-0d34-0410-b5e6-96231b3b80d8
804 lines
31 KiB
C++
804 lines
31 KiB
C++
//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the MSP430TargetLowering class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "msp430-lower"
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#include "MSP430ISelLowering.h"
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#include "MSP430.h"
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#include "MSP430TargetMachine.h"
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#include "MSP430Subtarget.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/CallingConv.h"
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#include "llvm/GlobalVariable.h"
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#include "llvm/GlobalAlias.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/VectorExtras.h"
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using namespace llvm;
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MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
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TargetLowering(tm, new TargetLoweringObjectFileELF()),
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Subtarget(*tm.getSubtargetImpl()), TM(tm) {
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// Set up the register classes.
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addRegisterClass(MVT::i8, MSP430::GR8RegisterClass);
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addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
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// Compute derived properties from the register classes
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computeRegisterProperties();
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// Provide all sorts of operation actions
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// Division is expensive
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setIntDivIsCheap(false);
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// Even if we have only 1 bit shift here, we can perform
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// shifts of the whole bitwidth 1 bit per step.
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setShiftAmountType(MVT::i8);
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setStackPointerRegisterToSaveRestore(MSP430::SPW);
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setBooleanContents(ZeroOrOneBooleanContent);
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setSchedulingPreference(SchedulingForLatency);
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// We have post-incremented loads / stores.
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setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
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setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
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setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
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setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
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// We don't have any truncstores
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setTruncStoreAction(MVT::i16, MVT::i8, Expand);
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setOperationAction(ISD::SRA, MVT::i8, Custom);
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setOperationAction(ISD::SHL, MVT::i8, Custom);
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setOperationAction(ISD::SRL, MVT::i8, Custom);
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setOperationAction(ISD::SRA, MVT::i16, Custom);
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setOperationAction(ISD::SHL, MVT::i16, Custom);
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setOperationAction(ISD::SRL, MVT::i16, Custom);
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setOperationAction(ISD::ROTL, MVT::i8, Expand);
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setOperationAction(ISD::ROTR, MVT::i8, Expand);
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setOperationAction(ISD::ROTL, MVT::i16, Expand);
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setOperationAction(ISD::ROTR, MVT::i16, Expand);
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setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
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setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::BRIND, MVT::Other, Expand);
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setOperationAction(ISD::BR_CC, MVT::i8, Custom);
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setOperationAction(ISD::BR_CC, MVT::i16, Custom);
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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setOperationAction(ISD::SETCC, MVT::i8, Expand);
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setOperationAction(ISD::SETCC, MVT::i16, Expand);
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setOperationAction(ISD::SELECT, MVT::i8, Expand);
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setOperationAction(ISD::SELECT, MVT::i16, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
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setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
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setOperationAction(ISD::CTTZ, MVT::i8, Expand);
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setOperationAction(ISD::CTTZ, MVT::i16, Expand);
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setOperationAction(ISD::CTLZ, MVT::i8, Expand);
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setOperationAction(ISD::CTLZ, MVT::i16, Expand);
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setOperationAction(ISD::CTPOP, MVT::i8, Expand);
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setOperationAction(ISD::CTPOP, MVT::i16, Expand);
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setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
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setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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// FIXME: Implement efficiently multiplication by a constant
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setOperationAction(ISD::MUL, MVT::i8, Expand);
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setOperationAction(ISD::MULHS, MVT::i8, Expand);
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setOperationAction(ISD::MULHU, MVT::i8, Expand);
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setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
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setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
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setOperationAction(ISD::MUL, MVT::i16, Expand);
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setOperationAction(ISD::MULHS, MVT::i16, Expand);
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setOperationAction(ISD::MULHU, MVT::i16, Expand);
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setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
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setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
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setOperationAction(ISD::UDIV, MVT::i8, Expand);
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setOperationAction(ISD::UDIVREM, MVT::i8, Expand);
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setOperationAction(ISD::UREM, MVT::i8, Expand);
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setOperationAction(ISD::SDIV, MVT::i8, Expand);
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setOperationAction(ISD::SDIVREM, MVT::i8, Expand);
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setOperationAction(ISD::SREM, MVT::i8, Expand);
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setOperationAction(ISD::UDIV, MVT::i16, Expand);
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setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
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setOperationAction(ISD::UREM, MVT::i16, Expand);
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setOperationAction(ISD::SDIV, MVT::i16, Expand);
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setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
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setOperationAction(ISD::SREM, MVT::i16, Expand);
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}
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SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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switch (Op.getOpcode()) {
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case ISD::SHL: // FALLTHROUGH
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case ISD::SRL:
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case ISD::SRA: return LowerShifts(Op, DAG);
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case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
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case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
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case ISD::BR_CC: return LowerBR_CC(Op, DAG);
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case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
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case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
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default:
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llvm_unreachable("unimplemented operand");
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return SDValue();
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}
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}
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/// getFunctionAlignment - Return the Log2 alignment of this function.
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unsigned MSP430TargetLowering::getFunctionAlignment(const Function *F) const {
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return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 2;
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}
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//===----------------------------------------------------------------------===//
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// MSP430 Inline Assembly Support
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//===----------------------------------------------------------------------===//
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/// getConstraintType - Given a constraint letter, return the type of
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/// constraint it is for this target.
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TargetLowering::ConstraintType
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MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
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if (Constraint.size() == 1) {
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switch (Constraint[0]) {
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case 'r':
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return C_RegisterClass;
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default:
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break;
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}
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}
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return TargetLowering::getConstraintType(Constraint);
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}
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std::pair<unsigned, const TargetRegisterClass*>
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MSP430TargetLowering::
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getRegForInlineAsmConstraint(const std::string &Constraint,
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EVT VT) const {
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if (Constraint.size() == 1) {
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// GCC Constraint Letters
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switch (Constraint[0]) {
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default: break;
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case 'r': // GENERAL_REGS
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if (VT == MVT::i8)
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return std::make_pair(0U, MSP430::GR8RegisterClass);
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return std::make_pair(0U, MSP430::GR16RegisterClass);
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}
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}
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return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
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}
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//===----------------------------------------------------------------------===//
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// Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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#include "MSP430GenCallingConv.inc"
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SDValue
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MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg>
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&Ins,
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DebugLoc dl,
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SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) {
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switch (CallConv) {
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default:
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llvm_unreachable("Unsupported calling convention");
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case CallingConv::C:
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case CallingConv::Fast:
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return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
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}
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}
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SDValue
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MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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CallingConv::ID CallConv, bool isVarArg,
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bool isTailCall,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) {
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switch (CallConv) {
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default:
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llvm_unreachable("Unsupported calling convention");
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case CallingConv::Fast:
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case CallingConv::C:
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return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
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Outs, Ins, dl, DAG, InVals);
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}
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}
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/// LowerCCCArguments - transform physical registers into virtual registers and
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/// generate load operations for arguments places on the stack.
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// FIXME: struct return stuff
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// FIXME: varargs
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SDValue
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MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
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CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg>
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&Ins,
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DebugLoc dl,
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SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) {
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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// Assign locations to all of the incoming arguments.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
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ArgLocs, *DAG.getContext());
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CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
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assert(!isVarArg && "Varargs not supported yet");
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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if (VA.isRegLoc()) {
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// Arguments passed in registers
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EVT RegVT = VA.getLocVT();
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switch (RegVT.getSimpleVT().SimpleTy) {
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default:
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{
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#ifndef NDEBUG
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errs() << "LowerFormalArguments Unhandled argument type: "
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<< RegVT.getSimpleVT().SimpleTy << "\n";
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#endif
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llvm_unreachable(0);
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}
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case MVT::i16:
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unsigned VReg =
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RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
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RegInfo.addLiveIn(VA.getLocReg(), VReg);
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SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
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// If this is an 8-bit value, it is really passed promoted to 16
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// bits. Insert an assert[sz]ext to capture this, then truncate to the
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// right size.
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if (VA.getLocInfo() == CCValAssign::SExt)
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ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
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DAG.getValueType(VA.getValVT()));
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else if (VA.getLocInfo() == CCValAssign::ZExt)
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ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
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DAG.getValueType(VA.getValVT()));
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if (VA.getLocInfo() != CCValAssign::Full)
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ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
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InVals.push_back(ArgValue);
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}
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} else {
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// Sanity check
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assert(VA.isMemLoc());
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// Load the argument to a virtual register
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unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
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if (ObjSize > 2) {
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errs() << "LowerFormalArguments Unhandled argument type: "
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<< VA.getLocVT().getSimpleVT().SimpleTy
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<< "\n";
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}
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// Create the frame index object for this incoming parameter...
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int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true, false);
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// Create the SelectionDAG nodes corresponding to a load
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//from this parameter
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SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
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InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
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PseudoSourceValue::getFixedStack(FI), 0));
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}
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}
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return Chain;
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}
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SDValue
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MSP430TargetLowering::LowerReturn(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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DebugLoc dl, SelectionDAG &DAG) {
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// CCValAssign - represent the assignment of the return value to a location
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SmallVector<CCValAssign, 16> RVLocs;
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// CCState - Info about the registers and stack slot.
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CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
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RVLocs, *DAG.getContext());
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// Analize return values.
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CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
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// If this is the first return lowered for this function, add the regs to the
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// liveout set for the function.
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if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
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for (unsigned i = 0; i != RVLocs.size(); ++i)
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if (RVLocs[i].isRegLoc())
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DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
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}
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SDValue Flag;
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// Copy the result values into the output registers.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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CCValAssign &VA = RVLocs[i];
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assert(VA.isRegLoc() && "Can only return in registers!");
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Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
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Outs[i].Val, Flag);
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// Guarantee that all emitted copies are stuck together,
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// avoiding something bad.
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Flag = Chain.getValue(1);
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}
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if (Flag.getNode())
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return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
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// Return Void
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return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain);
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}
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/// LowerCCCCallTo - functions arguments are copied from virtual regs to
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/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
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/// TODO: sret.
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SDValue
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MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
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CallingConv::ID CallConv, bool isVarArg,
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bool isTailCall,
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const SmallVectorImpl<ISD::OutputArg>
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&Outs,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) {
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// Analyze operands of the call, assigning locations to each operand.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
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ArgLocs, *DAG.getContext());
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CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
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// Get a count of how many bytes are to be pushed on the stack.
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unsigned NumBytes = CCInfo.getNextStackOffset();
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Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
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getPointerTy(), true));
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SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
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SmallVector<SDValue, 12> MemOpChains;
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SDValue StackPtr;
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// Walk the register/memloc assignments, inserting copies/loads.
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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SDValue Arg = Outs[i].Val;
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// Promote the value if needed.
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switch (VA.getLocInfo()) {
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default: llvm_unreachable("Unknown loc info!");
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case CCValAssign::Full: break;
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case CCValAssign::SExt:
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Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
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break;
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case CCValAssign::ZExt:
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Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
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break;
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case CCValAssign::AExt:
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Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
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break;
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}
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// Arguments that can be passed on register must be kept at RegsToPass
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// vector
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if (VA.isRegLoc()) {
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RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
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} else {
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assert(VA.isMemLoc());
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if (StackPtr.getNode() == 0)
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StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
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SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
|
|
StackPtr,
|
|
DAG.getIntPtrConstant(VA.getLocMemOffset()));
|
|
|
|
|
|
MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
|
|
PseudoSourceValue::getStack(),
|
|
VA.getLocMemOffset()));
|
|
}
|
|
}
|
|
|
|
// Transform all store nodes into one single node because all store nodes are
|
|
// independent of each other.
|
|
if (!MemOpChains.empty())
|
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
|
&MemOpChains[0], MemOpChains.size());
|
|
|
|
// Build a sequence of copy-to-reg nodes chained together with token chain and
|
|
// flag operands which copy the outgoing args into registers. The InFlag in
|
|
// necessary since all emited instructions must be stuck together.
|
|
SDValue InFlag;
|
|
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
|
|
Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
|
|
RegsToPass[i].second, InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
}
|
|
|
|
// If the callee is a GlobalAddress node (quite common, every direct call is)
|
|
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
|
|
// Likewise ExternalSymbol -> TargetExternalSymbol.
|
|
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
|
|
Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16);
|
|
else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
|
|
Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
|
|
|
|
// Returns a chain & a flag for retval copy to use.
|
|
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
|
|
SmallVector<SDValue, 8> Ops;
|
|
Ops.push_back(Chain);
|
|
Ops.push_back(Callee);
|
|
|
|
// Add argument registers to the end of the list so that they are
|
|
// known live into the call.
|
|
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
|
|
Ops.push_back(DAG.getRegister(RegsToPass[i].first,
|
|
RegsToPass[i].second.getValueType()));
|
|
|
|
if (InFlag.getNode())
|
|
Ops.push_back(InFlag);
|
|
|
|
Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
|
|
InFlag = Chain.getValue(1);
|
|
|
|
// Create the CALLSEQ_END node.
|
|
Chain = DAG.getCALLSEQ_END(Chain,
|
|
DAG.getConstant(NumBytes, getPointerTy(), true),
|
|
DAG.getConstant(0, getPointerTy(), true),
|
|
InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
|
|
// Handle result values, copying them out of physregs into vregs that we
|
|
// return.
|
|
return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
|
|
DAG, InVals);
|
|
}
|
|
|
|
/// LowerCallResult - Lower the result values of a call into the
|
|
/// appropriate copies out of appropriate physical registers.
|
|
///
|
|
SDValue
|
|
MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
DebugLoc dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) {
|
|
|
|
// Assign locations to each value returned by this call.
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
|
CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
|
|
RVLocs, *DAG.getContext());
|
|
|
|
CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430);
|
|
|
|
// Copy all of the result registers out of their specified physreg.
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
|
Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
|
|
RVLocs[i].getValVT(), InFlag).getValue(1);
|
|
InFlag = Chain.getValue(2);
|
|
InVals.push_back(Chain.getValue(0));
|
|
}
|
|
|
|
return Chain;
|
|
}
|
|
|
|
SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
|
|
SelectionDAG &DAG) {
|
|
unsigned Opc = Op.getOpcode();
|
|
SDNode* N = Op.getNode();
|
|
EVT VT = Op.getValueType();
|
|
DebugLoc dl = N->getDebugLoc();
|
|
|
|
// We currently only lower shifts of constant argument.
|
|
if (!isa<ConstantSDNode>(N->getOperand(1)))
|
|
return SDValue();
|
|
|
|
uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
|
|
|
|
// Expand the stuff into sequence of shifts.
|
|
// FIXME: for some shift amounts this might be done better!
|
|
// E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
|
|
SDValue Victim = N->getOperand(0);
|
|
|
|
if (Opc == ISD::SRL && ShiftAmount) {
|
|
// Emit a special goodness here:
|
|
// srl A, 1 => clrc; rrc A
|
|
Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
|
|
ShiftAmount -= 1;
|
|
}
|
|
|
|
while (ShiftAmount--)
|
|
Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
|
|
dl, VT, Victim);
|
|
|
|
return Victim;
|
|
}
|
|
|
|
SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
|
|
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
|
|
int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
|
|
|
|
// Create the TargetGlobalAddress node, folding in the constant offset.
|
|
SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
|
|
return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
|
|
getPointerTy(), Result);
|
|
}
|
|
|
|
SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
|
|
SelectionDAG &DAG) {
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
|
|
SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
|
|
|
|
return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
|
|
}
|
|
|
|
static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
|
|
ISD::CondCode CC,
|
|
DebugLoc dl, SelectionDAG &DAG) {
|
|
// FIXME: Handle bittests someday
|
|
assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
|
|
|
|
// FIXME: Handle jump negative someday
|
|
MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
|
|
switch (CC) {
|
|
default: llvm_unreachable("Invalid integer condition!");
|
|
case ISD::SETEQ:
|
|
TCC = MSP430CC::COND_E; // aka COND_Z
|
|
// Minor optimization: if RHS is a constant, swap operands, then the
|
|
// constant can be folded into comparison.
|
|
if (RHS.getOpcode() == ISD::Constant)
|
|
std::swap(LHS, RHS);
|
|
break;
|
|
case ISD::SETNE:
|
|
TCC = MSP430CC::COND_NE; // aka COND_NZ
|
|
// Minor optimization: if RHS is a constant, swap operands, then the
|
|
// constant can be folded into comparison.
|
|
if (RHS.getOpcode() == ISD::Constant)
|
|
std::swap(LHS, RHS);
|
|
break;
|
|
case ISD::SETULE:
|
|
std::swap(LHS, RHS); // FALLTHROUGH
|
|
case ISD::SETUGE:
|
|
TCC = MSP430CC::COND_HS; // aka COND_C
|
|
break;
|
|
case ISD::SETUGT:
|
|
std::swap(LHS, RHS); // FALLTHROUGH
|
|
case ISD::SETULT:
|
|
TCC = MSP430CC::COND_LO; // aka COND_NC
|
|
break;
|
|
case ISD::SETLE:
|
|
std::swap(LHS, RHS); // FALLTHROUGH
|
|
case ISD::SETGE:
|
|
TCC = MSP430CC::COND_GE;
|
|
break;
|
|
case ISD::SETGT:
|
|
std::swap(LHS, RHS); // FALLTHROUGH
|
|
case ISD::SETLT:
|
|
TCC = MSP430CC::COND_L;
|
|
break;
|
|
}
|
|
|
|
TargetCC = DAG.getConstant(TCC, MVT::i8);
|
|
return DAG.getNode(MSP430ISD::CMP, dl, MVT::Flag, LHS, RHS);
|
|
}
|
|
|
|
|
|
SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
|
|
SDValue Chain = Op.getOperand(0);
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
|
|
SDValue LHS = Op.getOperand(2);
|
|
SDValue RHS = Op.getOperand(3);
|
|
SDValue Dest = Op.getOperand(4);
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
SDValue TargetCC;
|
|
SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
|
|
|
|
return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
|
|
Chain, Dest, TargetCC, Flag);
|
|
}
|
|
|
|
SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
|
|
SDValue LHS = Op.getOperand(0);
|
|
SDValue RHS = Op.getOperand(1);
|
|
SDValue TrueV = Op.getOperand(2);
|
|
SDValue FalseV = Op.getOperand(3);
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
SDValue TargetCC;
|
|
SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
|
|
|
|
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
|
|
SmallVector<SDValue, 4> Ops;
|
|
Ops.push_back(TrueV);
|
|
Ops.push_back(FalseV);
|
|
Ops.push_back(TargetCC);
|
|
Ops.push_back(Flag);
|
|
|
|
return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
|
|
}
|
|
|
|
SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
|
|
SelectionDAG &DAG) {
|
|
SDValue Val = Op.getOperand(0);
|
|
EVT VT = Op.getValueType();
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
assert(VT == MVT::i16 && "Only support i16 for now!");
|
|
|
|
return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
|
|
DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
|
|
DAG.getValueType(Val.getValueType()));
|
|
}
|
|
|
|
/// getPostIndexedAddressParts - returns true by value, base pointer and
|
|
/// offset pointer and addressing mode by reference if this node can be
|
|
/// combined with a load / store to form a post-indexed load / store.
|
|
bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
|
|
SDValue &Base,
|
|
SDValue &Offset,
|
|
ISD::MemIndexedMode &AM,
|
|
SelectionDAG &DAG) const {
|
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(N);
|
|
if (LD->getExtensionType() != ISD::NON_EXTLOAD)
|
|
return false;
|
|
|
|
EVT VT = LD->getMemoryVT();
|
|
if (VT != MVT::i8 && VT != MVT::i16)
|
|
return false;
|
|
|
|
if (Op->getOpcode() != ISD::ADD)
|
|
return false;
|
|
|
|
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
|
|
uint64_t RHSC = RHS->getZExtValue();
|
|
if ((VT == MVT::i16 && RHSC != 2) ||
|
|
(VT == MVT::i8 && RHSC != 1))
|
|
return false;
|
|
|
|
Base = Op->getOperand(0);
|
|
Offset = DAG.getConstant(RHSC, VT);
|
|
AM = ISD::POST_INC;
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
|
|
const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
|
|
switch (Opcode) {
|
|
default: return NULL;
|
|
case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG";
|
|
case MSP430ISD::RRA: return "MSP430ISD::RRA";
|
|
case MSP430ISD::RLA: return "MSP430ISD::RLA";
|
|
case MSP430ISD::RRC: return "MSP430ISD::RRC";
|
|
case MSP430ISD::CALL: return "MSP430ISD::CALL";
|
|
case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper";
|
|
case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC";
|
|
case MSP430ISD::CMP: return "MSP430ISD::CMP";
|
|
case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC";
|
|
}
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Other Lowering Code
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
MachineBasicBlock*
|
|
MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|
MachineBasicBlock *BB,
|
|
DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
|
|
const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
|
|
DebugLoc dl = MI->getDebugLoc();
|
|
assert((MI->getOpcode() == MSP430::Select16 ||
|
|
MI->getOpcode() == MSP430::Select8) &&
|
|
"Unexpected instr type to insert");
|
|
|
|
// To "insert" a SELECT instruction, we actually have to insert the diamond
|
|
// control-flow pattern. The incoming instruction knows the destination vreg
|
|
// to set, the condition code register to branch on, the true/false values to
|
|
// select between, and a branch opcode to use.
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
MachineFunction::iterator I = BB;
|
|
++I;
|
|
|
|
// thisMBB:
|
|
// ...
|
|
// TrueVal = ...
|
|
// cmpTY ccX, r1, r2
|
|
// jCC copy1MBB
|
|
// fallthrough --> copy0MBB
|
|
MachineBasicBlock *thisMBB = BB;
|
|
MachineFunction *F = BB->getParent();
|
|
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
BuildMI(BB, dl, TII.get(MSP430::JCC))
|
|
.addMBB(copy1MBB)
|
|
.addImm(MI->getOperand(3).getImm());
|
|
F->insert(I, copy0MBB);
|
|
F->insert(I, copy1MBB);
|
|
// Inform sdisel of the edge changes.
|
|
for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
|
|
SE = BB->succ_end(); SI != SE; ++SI)
|
|
EM->insert(std::make_pair(*SI, copy1MBB));
|
|
// Update machine-CFG edges by transferring all successors of the current
|
|
// block to the new block which will contain the Phi node for the select.
|
|
copy1MBB->transferSuccessors(BB);
|
|
// Next, add the true and fallthrough blocks as its successors.
|
|
BB->addSuccessor(copy0MBB);
|
|
BB->addSuccessor(copy1MBB);
|
|
|
|
// copy0MBB:
|
|
// %FalseValue = ...
|
|
// # fallthrough to copy1MBB
|
|
BB = copy0MBB;
|
|
|
|
// Update machine-CFG edges
|
|
BB->addSuccessor(copy1MBB);
|
|
|
|
// copy1MBB:
|
|
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
|
|
// ...
|
|
BB = copy1MBB;
|
|
BuildMI(BB, dl, TII.get(MSP430::PHI),
|
|
MI->getOperand(0).getReg())
|
|
.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
|
|
.addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
|
|
|
|
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
|
|
return BB;
|
|
}
|