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llvm-6502/lib/Target/Alpha
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Dan Gohman 533297b58d Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-29 18:10:34 +00:00
..
AsmPrinter Remove includes of Support/Compiler.h that are no longer needed after the 2009-10-25 06:57:41 +00:00
TargetInfo
Alpha.h
Alpha.td
AlphaBranchSelector.cpp Remove includes of Support/Compiler.h that are no longer needed after the 2009-10-25 06:57:41 +00:00
AlphaCallingConv.td
AlphaCodeEmitter.cpp Remove includes of Support/Compiler.h that are no longer needed after the 2009-10-25 06:57:41 +00:00
AlphaInstrFormats.td
AlphaInstrInfo.cpp
AlphaInstrInfo.h
AlphaInstrInfo.td Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 2009-10-29 18:10:34 +00:00
AlphaISelDAGToDAG.cpp Rename getTargetNode to getMachineNode, for consistency with the 2009-09-25 18:54:59 +00:00
AlphaISelLowering.cpp Add a second ValueType argument to isFPImmLegal. 2009-10-28 01:43:28 +00:00
AlphaISelLowering.h Add a second ValueType argument to isFPImmLegal. 2009-10-28 01:43:28 +00:00
AlphaJITInfo.cpp
AlphaJITInfo.h
AlphaLLRP.cpp
AlphaMachineFunctionInfo.h
AlphaMCAsmInfo.cpp
AlphaMCAsmInfo.h
AlphaRegisterInfo.cpp Add register-reuse to frame-index register scavenging. When a target uses 2009-10-07 17:12:56 +00:00
AlphaRegisterInfo.h Add register-reuse to frame-index register scavenging. When a target uses 2009-10-07 17:12:56 +00:00
AlphaRegisterInfo.td
AlphaRelocations.h
AlphaSchedule.td
AlphaSubtarget.cpp
AlphaSubtarget.h
AlphaTargetMachine.cpp
AlphaTargetMachine.h
CMakeLists.txt
Makefile
README.txt

README.txt 

***

add gcc builtins for alpha instructions


***

custom expand byteswap into nifty 
extract/insert/mask byte/word/longword/quadword low/high
sequences

***

see if any of the extract/insert/mask operations can be added

***

match more interesting things for cmovlbc cmovlbs (move if low bit clear/set)

***

lower srem and urem

remq(i,j):  i - (j * divq(i,j)) if j != 0
remqu(i,j): i - (j * divqu(i,j)) if j != 0
reml(i,j):  i - (j * divl(i,j)) if j != 0
remlu(i,j): i - (j * divlu(i,j)) if j != 0

***

add crazy vector instructions (MVI):

(MIN|MAX)(U|S)(B8|W4) min and max, signed and unsigned, byte and word
PKWB, UNPKBW pack/unpack word to byte
PKLB UNPKBL pack/unpack long to byte
PERR pixel error (sum accross bytes of bytewise abs(i8v8 a - i8v8 b))

cmpbytes bytewise cmpeq of i8v8 a and i8v8 b (not part of MVI extentions)

this has some good examples for other operations that can be synthesised well 
from these rather meager vector ops (such as saturating add).
http://www.alphalinux.org/docs/MVI-full.html