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Shaves 200k off Release-Asserts clang binaries on i386. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142191 91177308-0d34-0410-b5e6-96231b3b80d8
2459 lines
88 KiB
C++
2459 lines
88 KiB
C++
//===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend emits a target specifier matcher for converting parsed
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// assembly operands in the MCInst structures. It also emits a matcher for
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// custom operand parsing.
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//
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// Converting assembly operands into MCInst structures
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// ---------------------------------------------------
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//
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// The input to the target specific matcher is a list of literal tokens and
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// operands. The target specific parser should generally eliminate any syntax
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// which is not relevant for matching; for example, comma tokens should have
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// already been consumed and eliminated by the parser. Most instructions will
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// end up with a single literal token (the instruction name) and some number of
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// operands.
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//
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// Some example inputs, for X86:
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// 'addl' (immediate ...) (register ...)
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// 'add' (immediate ...) (memory ...)
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// 'call' '*' %epc
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//
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// The assembly matcher is responsible for converting this input into a precise
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// machine instruction (i.e., an instruction with a well defined encoding). This
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// mapping has several properties which complicate matching:
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//
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// - It may be ambiguous; many architectures can legally encode particular
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// variants of an instruction in different ways (for example, using a smaller
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// encoding for small immediates). Such ambiguities should never be
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// arbitrarily resolved by the assembler, the assembler is always responsible
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// for choosing the "best" available instruction.
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//
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// - It may depend on the subtarget or the assembler context. Instructions
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// which are invalid for the current mode, but otherwise unambiguous (e.g.,
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// an SSE instruction in a file being assembled for i486) should be accepted
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// and rejected by the assembler front end. However, if the proper encoding
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// for an instruction is dependent on the assembler context then the matcher
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// is responsible for selecting the correct machine instruction for the
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// current mode.
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//
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// The core matching algorithm attempts to exploit the regularity in most
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// instruction sets to quickly determine the set of possibly matching
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// instructions, and the simplify the generated code. Additionally, this helps
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// to ensure that the ambiguities are intentionally resolved by the user.
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//
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// The matching is divided into two distinct phases:
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//
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// 1. Classification: Each operand is mapped to the unique set which (a)
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// contains it, and (b) is the largest such subset for which a single
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// instruction could match all members.
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//
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// For register classes, we can generate these subgroups automatically. For
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// arbitrary operands, we expect the user to define the classes and their
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// relations to one another (for example, 8-bit signed immediates as a
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// subset of 32-bit immediates).
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//
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// By partitioning the operands in this way, we guarantee that for any
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// tuple of classes, any single instruction must match either all or none
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// of the sets of operands which could classify to that tuple.
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//
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// In addition, the subset relation amongst classes induces a partial order
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// on such tuples, which we use to resolve ambiguities.
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//
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// 2. The input can now be treated as a tuple of classes (static tokens are
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// simple singleton sets). Each such tuple should generally map to a single
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// instruction (we currently ignore cases where this isn't true, whee!!!),
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// which we can emit a simple matcher for.
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//
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// Custom Operand Parsing
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// ----------------------
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//
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// Some targets need a custom way to parse operands, some specific instructions
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// can contain arguments that can represent processor flags and other kinds of
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// identifiers that need to be mapped to specific valeus in the final encoded
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// instructions. The target specific custom operand parsing works in the
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// following way:
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//
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// 1. A operand match table is built, each entry contains a mnemonic, an
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// operand class, a mask for all operand positions for that same
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// class/mnemonic and target features to be checked while trying to match.
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//
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// 2. The operand matcher will try every possible entry with the same
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// mnemonic and will check if the target feature for this mnemonic also
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// matches. After that, if the operand to be matched has its index
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// present in the mask, a successful match occurs. Otherwise, fallback
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// to the regular operand parsing.
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//
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// 3. For a match success, each operand class that has a 'ParserMethod'
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// becomes part of a switch from where the custom method is called.
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//
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//===----------------------------------------------------------------------===//
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#include "AsmMatcherEmitter.h"
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#include "CodeGenTarget.h"
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#include "StringMatcher.h"
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#include "llvm/ADT/OwningPtr.h"
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#include "llvm/ADT/PointerUnion.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/Record.h"
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#include <map>
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#include <set>
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using namespace llvm;
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static cl::opt<std::string>
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MatchPrefix("match-prefix", cl::init(""),
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cl::desc("Only match instructions with the given prefix"));
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namespace {
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class AsmMatcherInfo;
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struct SubtargetFeatureInfo;
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/// ClassInfo - Helper class for storing the information about a particular
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/// class of operands which can be matched.
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struct ClassInfo {
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enum ClassInfoKind {
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/// Invalid kind, for use as a sentinel value.
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Invalid = 0,
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/// The class for a particular token.
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Token,
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/// The (first) register class, subsequent register classes are
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/// RegisterClass0+1, and so on.
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RegisterClass0,
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/// The (first) user defined class, subsequent user defined classes are
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/// UserClass0+1, and so on.
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UserClass0 = 1<<16
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};
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/// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
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/// N) for the Nth user defined class.
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unsigned Kind;
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/// SuperClasses - The super classes of this class. Note that for simplicities
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/// sake user operands only record their immediate super class, while register
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/// operands include all superclasses.
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std::vector<ClassInfo*> SuperClasses;
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/// Name - The full class name, suitable for use in an enum.
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std::string Name;
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/// ClassName - The unadorned generic name for this class (e.g., Token).
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std::string ClassName;
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/// ValueName - The name of the value this class represents; for a token this
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/// is the literal token string, for an operand it is the TableGen class (or
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/// empty if this is a derived class).
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std::string ValueName;
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/// PredicateMethod - The name of the operand method to test whether the
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/// operand matches this class; this is not valid for Token or register kinds.
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std::string PredicateMethod;
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/// RenderMethod - The name of the operand method to add this operand to an
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/// MCInst; this is not valid for Token or register kinds.
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std::string RenderMethod;
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/// ParserMethod - The name of the operand method to do a target specific
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/// parsing on the operand.
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std::string ParserMethod;
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/// For register classes, the records for all the registers in this class.
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std::set<Record*> Registers;
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public:
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/// isRegisterClass() - Check if this is a register class.
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bool isRegisterClass() const {
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return Kind >= RegisterClass0 && Kind < UserClass0;
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}
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/// isUserClass() - Check if this is a user defined class.
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bool isUserClass() const {
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return Kind >= UserClass0;
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}
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/// isRelatedTo - Check whether this class is "related" to \arg RHS. Classes
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/// are related if they are in the same class hierarchy.
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bool isRelatedTo(const ClassInfo &RHS) const {
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// Tokens are only related to tokens.
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if (Kind == Token || RHS.Kind == Token)
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return Kind == Token && RHS.Kind == Token;
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// Registers classes are only related to registers classes, and only if
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// their intersection is non-empty.
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if (isRegisterClass() || RHS.isRegisterClass()) {
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if (!isRegisterClass() || !RHS.isRegisterClass())
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return false;
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std::set<Record*> Tmp;
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std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin());
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std::set_intersection(Registers.begin(), Registers.end(),
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RHS.Registers.begin(), RHS.Registers.end(),
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II);
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return !Tmp.empty();
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}
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// Otherwise we have two users operands; they are related if they are in the
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// same class hierarchy.
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//
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// FIXME: This is an oversimplification, they should only be related if they
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// intersect, however we don't have that information.
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assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
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const ClassInfo *Root = this;
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while (!Root->SuperClasses.empty())
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Root = Root->SuperClasses.front();
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const ClassInfo *RHSRoot = &RHS;
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while (!RHSRoot->SuperClasses.empty())
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RHSRoot = RHSRoot->SuperClasses.front();
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return Root == RHSRoot;
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}
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/// isSubsetOf - Test whether this class is a subset of \arg RHS;
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bool isSubsetOf(const ClassInfo &RHS) const {
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// This is a subset of RHS if it is the same class...
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if (this == &RHS)
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return true;
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// ... or if any of its super classes are a subset of RHS.
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for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
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ie = SuperClasses.end(); it != ie; ++it)
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if ((*it)->isSubsetOf(RHS))
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return true;
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return false;
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}
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/// operator< - Compare two classes.
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bool operator<(const ClassInfo &RHS) const {
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if (this == &RHS)
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return false;
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// Unrelated classes can be ordered by kind.
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if (!isRelatedTo(RHS))
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return Kind < RHS.Kind;
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switch (Kind) {
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case Invalid:
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assert(0 && "Invalid kind!");
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case Token:
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// Tokens are comparable by value.
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//
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// FIXME: Compare by enum value.
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return ValueName < RHS.ValueName;
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default:
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// This class precedes the RHS if it is a proper subset of the RHS.
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if (isSubsetOf(RHS))
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return true;
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if (RHS.isSubsetOf(*this))
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return false;
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// Otherwise, order by name to ensure we have a total ordering.
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return ValueName < RHS.ValueName;
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}
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}
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};
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/// MatchableInfo - Helper class for storing the necessary information for an
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/// instruction or alias which is capable of being matched.
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struct MatchableInfo {
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struct AsmOperand {
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/// Token - This is the token that the operand came from.
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StringRef Token;
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/// The unique class instance this operand should match.
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ClassInfo *Class;
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/// The operand name this is, if anything.
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StringRef SrcOpName;
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/// The suboperand index within SrcOpName, or -1 for the entire operand.
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int SubOpIdx;
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explicit AsmOperand(StringRef T) : Token(T), Class(0), SubOpIdx(-1) {}
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};
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/// ResOperand - This represents a single operand in the result instruction
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/// generated by the match. In cases (like addressing modes) where a single
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/// assembler operand expands to multiple MCOperands, this represents the
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/// single assembler operand, not the MCOperand.
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struct ResOperand {
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enum {
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/// RenderAsmOperand - This represents an operand result that is
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/// generated by calling the render method on the assembly operand. The
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/// corresponding AsmOperand is specified by AsmOperandNum.
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RenderAsmOperand,
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/// TiedOperand - This represents a result operand that is a duplicate of
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/// a previous result operand.
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TiedOperand,
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/// ImmOperand - This represents an immediate value that is dumped into
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/// the operand.
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ImmOperand,
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/// RegOperand - This represents a fixed register that is dumped in.
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RegOperand
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} Kind;
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union {
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/// This is the operand # in the AsmOperands list that this should be
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/// copied from.
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unsigned AsmOperandNum;
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/// TiedOperandNum - This is the (earlier) result operand that should be
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/// copied from.
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unsigned TiedOperandNum;
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/// ImmVal - This is the immediate value added to the instruction.
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int64_t ImmVal;
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/// Register - This is the register record.
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Record *Register;
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};
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/// MINumOperands - The number of MCInst operands populated by this
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/// operand.
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unsigned MINumOperands;
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static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
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ResOperand X;
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X.Kind = RenderAsmOperand;
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X.AsmOperandNum = AsmOpNum;
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X.MINumOperands = NumOperands;
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return X;
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}
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static ResOperand getTiedOp(unsigned TiedOperandNum) {
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ResOperand X;
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X.Kind = TiedOperand;
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X.TiedOperandNum = TiedOperandNum;
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X.MINumOperands = 1;
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return X;
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}
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static ResOperand getImmOp(int64_t Val) {
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ResOperand X;
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X.Kind = ImmOperand;
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X.ImmVal = Val;
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X.MINumOperands = 1;
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return X;
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}
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static ResOperand getRegOp(Record *Reg) {
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ResOperand X;
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X.Kind = RegOperand;
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X.Register = Reg;
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X.MINumOperands = 1;
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return X;
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}
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};
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/// TheDef - This is the definition of the instruction or InstAlias that this
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/// matchable came from.
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Record *const TheDef;
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/// DefRec - This is the definition that it came from.
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PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
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const CodeGenInstruction *getResultInst() const {
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if (DefRec.is<const CodeGenInstruction*>())
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return DefRec.get<const CodeGenInstruction*>();
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return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
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}
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/// ResOperands - This is the operand list that should be built for the result
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/// MCInst.
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std::vector<ResOperand> ResOperands;
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/// AsmString - The assembly string for this instruction (with variants
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/// removed), e.g. "movsx $src, $dst".
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std::string AsmString;
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/// Mnemonic - This is the first token of the matched instruction, its
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/// mnemonic.
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StringRef Mnemonic;
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/// AsmOperands - The textual operands that this instruction matches,
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/// annotated with a class and where in the OperandList they were defined.
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/// This directly corresponds to the tokenized AsmString after the mnemonic is
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/// removed.
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SmallVector<AsmOperand, 4> AsmOperands;
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/// Predicates - The required subtarget features to match this instruction.
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SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
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/// ConversionFnKind - The enum value which is passed to the generated
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/// ConvertToMCInst to convert parsed operands into an MCInst for this
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/// function.
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std::string ConversionFnKind;
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MatchableInfo(const CodeGenInstruction &CGI)
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: TheDef(CGI.TheDef), DefRec(&CGI), AsmString(CGI.AsmString) {
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}
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MatchableInfo(const CodeGenInstAlias *Alias)
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: TheDef(Alias->TheDef), DefRec(Alias), AsmString(Alias->AsmString) {
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}
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void Initialize(const AsmMatcherInfo &Info,
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SmallPtrSet<Record*, 16> &SingletonRegisters);
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/// Validate - Return true if this matchable is a valid thing to match against
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/// and perform a bunch of validity checking.
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bool Validate(StringRef CommentDelimiter, bool Hack) const;
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/// getSingletonRegisterForAsmOperand - If the specified token is a singleton
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/// register, return the Record for it, otherwise return null.
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Record *getSingletonRegisterForAsmOperand(unsigned i,
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const AsmMatcherInfo &Info) const;
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/// FindAsmOperand - Find the AsmOperand with the specified name and
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/// suboperand index.
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int FindAsmOperand(StringRef N, int SubOpIdx) const {
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for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
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if (N == AsmOperands[i].SrcOpName &&
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SubOpIdx == AsmOperands[i].SubOpIdx)
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return i;
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return -1;
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}
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/// FindAsmOperandNamed - Find the first AsmOperand with the specified name.
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/// This does not check the suboperand index.
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int FindAsmOperandNamed(StringRef N) const {
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for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
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if (N == AsmOperands[i].SrcOpName)
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return i;
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return -1;
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}
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void BuildInstructionResultOperands();
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void BuildAliasResultOperands();
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/// operator< - Compare two matchables.
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bool operator<(const MatchableInfo &RHS) const {
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// The primary comparator is the instruction mnemonic.
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if (Mnemonic != RHS.Mnemonic)
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return Mnemonic < RHS.Mnemonic;
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if (AsmOperands.size() != RHS.AsmOperands.size())
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return AsmOperands.size() < RHS.AsmOperands.size();
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// Compare lexicographically by operand. The matcher validates that other
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// orderings wouldn't be ambiguous using \see CouldMatchAmbiguouslyWith().
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for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
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if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
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return true;
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if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
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return false;
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}
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return false;
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}
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/// CouldMatchAmbiguouslyWith - Check whether this matchable could
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/// ambiguously match the same set of operands as \arg RHS (without being a
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/// strictly superior match).
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bool CouldMatchAmbiguouslyWith(const MatchableInfo &RHS) {
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// The primary comparator is the instruction mnemonic.
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if (Mnemonic != RHS.Mnemonic)
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return false;
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// The number of operands is unambiguous.
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if (AsmOperands.size() != RHS.AsmOperands.size())
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return false;
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// Otherwise, make sure the ordering of the two instructions is unambiguous
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// by checking that either (a) a token or operand kind discriminates them,
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// or (b) the ordering among equivalent kinds is consistent.
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// Tokens and operand kinds are unambiguous (assuming a correct target
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// specific parser).
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for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
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if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
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AsmOperands[i].Class->Kind == ClassInfo::Token)
|
|
if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
|
|
*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
|
|
return false;
|
|
|
|
// Otherwise, this operand could commute if all operands are equivalent, or
|
|
// there is a pair of operands that compare less than and a pair that
|
|
// compare greater than.
|
|
bool HasLT = false, HasGT = false;
|
|
for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
|
|
if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
|
|
HasLT = true;
|
|
if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
|
|
HasGT = true;
|
|
}
|
|
|
|
return !(HasLT ^ HasGT);
|
|
}
|
|
|
|
void dump();
|
|
|
|
private:
|
|
void TokenizeAsmString(const AsmMatcherInfo &Info);
|
|
};
|
|
|
|
/// SubtargetFeatureInfo - Helper class for storing information on a subtarget
|
|
/// feature which participates in instruction matching.
|
|
struct SubtargetFeatureInfo {
|
|
/// \brief The predicate record for this feature.
|
|
Record *TheDef;
|
|
|
|
/// \brief An unique index assigned to represent this feature.
|
|
unsigned Index;
|
|
|
|
SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
|
|
|
|
/// \brief The name of the enumerated constant identifying this feature.
|
|
std::string getEnumName() const {
|
|
return "Feature_" + TheDef->getName();
|
|
}
|
|
};
|
|
|
|
struct OperandMatchEntry {
|
|
unsigned OperandMask;
|
|
MatchableInfo* MI;
|
|
ClassInfo *CI;
|
|
|
|
static OperandMatchEntry Create(MatchableInfo* mi, ClassInfo *ci,
|
|
unsigned opMask) {
|
|
OperandMatchEntry X;
|
|
X.OperandMask = opMask;
|
|
X.CI = ci;
|
|
X.MI = mi;
|
|
return X;
|
|
}
|
|
};
|
|
|
|
|
|
class AsmMatcherInfo {
|
|
public:
|
|
/// Tracked Records
|
|
RecordKeeper &Records;
|
|
|
|
/// The tablegen AsmParser record.
|
|
Record *AsmParser;
|
|
|
|
/// Target - The target information.
|
|
CodeGenTarget &Target;
|
|
|
|
/// The AsmParser "RegisterPrefix" value.
|
|
std::string RegisterPrefix;
|
|
|
|
/// The classes which are needed for matching.
|
|
std::vector<ClassInfo*> Classes;
|
|
|
|
/// The information on the matchables to match.
|
|
std::vector<MatchableInfo*> Matchables;
|
|
|
|
/// Info for custom matching operands by user defined methods.
|
|
std::vector<OperandMatchEntry> OperandMatchInfo;
|
|
|
|
/// Map of Register records to their class information.
|
|
std::map<Record*, ClassInfo*> RegisterClasses;
|
|
|
|
/// Map of Predicate records to their subtarget information.
|
|
std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures;
|
|
|
|
private:
|
|
/// Map of token to class information which has already been constructed.
|
|
std::map<std::string, ClassInfo*> TokenClasses;
|
|
|
|
/// Map of RegisterClass records to their class information.
|
|
std::map<Record*, ClassInfo*> RegisterClassClasses;
|
|
|
|
/// Map of AsmOperandClass records to their class information.
|
|
std::map<Record*, ClassInfo*> AsmOperandClasses;
|
|
|
|
private:
|
|
/// getTokenClass - Lookup or create the class for the given token.
|
|
ClassInfo *getTokenClass(StringRef Token);
|
|
|
|
/// getOperandClass - Lookup or create the class for the given operand.
|
|
ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
|
|
int SubOpIdx = -1);
|
|
|
|
/// BuildRegisterClasses - Build the ClassInfo* instances for register
|
|
/// classes.
|
|
void BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters);
|
|
|
|
/// BuildOperandClasses - Build the ClassInfo* instances for user defined
|
|
/// operand classes.
|
|
void BuildOperandClasses();
|
|
|
|
void BuildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
|
|
unsigned AsmOpIdx);
|
|
void BuildAliasOperandReference(MatchableInfo *II, StringRef OpName,
|
|
MatchableInfo::AsmOperand &Op);
|
|
|
|
public:
|
|
AsmMatcherInfo(Record *AsmParser,
|
|
CodeGenTarget &Target,
|
|
RecordKeeper &Records);
|
|
|
|
/// BuildInfo - Construct the various tables used during matching.
|
|
void BuildInfo();
|
|
|
|
/// BuildOperandMatchInfo - Build the necessary information to handle user
|
|
/// defined operand parsing methods.
|
|
void BuildOperandMatchInfo();
|
|
|
|
/// getSubtargetFeature - Lookup or create the subtarget feature info for the
|
|
/// given operand.
|
|
SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
|
|
assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
|
|
std::map<Record*, SubtargetFeatureInfo*>::const_iterator I =
|
|
SubtargetFeatures.find(Def);
|
|
return I == SubtargetFeatures.end() ? 0 : I->second;
|
|
}
|
|
|
|
RecordKeeper &getRecords() const {
|
|
return Records;
|
|
}
|
|
};
|
|
|
|
}
|
|
|
|
void MatchableInfo::dump() {
|
|
errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
|
|
|
|
for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
|
|
AsmOperand &Op = AsmOperands[i];
|
|
errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
|
|
errs() << '\"' << Op.Token << "\"\n";
|
|
}
|
|
}
|
|
|
|
void MatchableInfo::Initialize(const AsmMatcherInfo &Info,
|
|
SmallPtrSet<Record*, 16> &SingletonRegisters) {
|
|
// TODO: Eventually support asmparser for Variant != 0.
|
|
AsmString = CodeGenInstruction::FlattenAsmStringVariants(AsmString, 0);
|
|
|
|
TokenizeAsmString(Info);
|
|
|
|
// Compute the require features.
|
|
std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
|
|
for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
|
|
if (SubtargetFeatureInfo *Feature =
|
|
Info.getSubtargetFeature(Predicates[i]))
|
|
RequiredFeatures.push_back(Feature);
|
|
|
|
// Collect singleton registers, if used.
|
|
for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
|
|
if (Record *Reg = getSingletonRegisterForAsmOperand(i, Info))
|
|
SingletonRegisters.insert(Reg);
|
|
}
|
|
}
|
|
|
|
/// TokenizeAsmString - Tokenize a simplified assembly string.
|
|
void MatchableInfo::TokenizeAsmString(const AsmMatcherInfo &Info) {
|
|
StringRef String = AsmString;
|
|
unsigned Prev = 0;
|
|
bool InTok = true;
|
|
for (unsigned i = 0, e = String.size(); i != e; ++i) {
|
|
switch (String[i]) {
|
|
case '[':
|
|
case ']':
|
|
case '*':
|
|
case '!':
|
|
case ' ':
|
|
case '\t':
|
|
case ',':
|
|
if (InTok) {
|
|
AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
|
|
InTok = false;
|
|
}
|
|
if (!isspace(String[i]) && String[i] != ',')
|
|
AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
|
|
Prev = i + 1;
|
|
break;
|
|
|
|
case '\\':
|
|
if (InTok) {
|
|
AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
|
|
InTok = false;
|
|
}
|
|
++i;
|
|
assert(i != String.size() && "Invalid quoted character");
|
|
AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
|
|
Prev = i + 1;
|
|
break;
|
|
|
|
case '$': {
|
|
if (InTok) {
|
|
AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
|
|
InTok = false;
|
|
}
|
|
|
|
// If this isn't "${", treat like a normal token.
|
|
if (i + 1 == String.size() || String[i + 1] != '{') {
|
|
Prev = i;
|
|
break;
|
|
}
|
|
|
|
StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
|
|
assert(End != String.end() && "Missing brace in operand reference!");
|
|
size_t EndPos = End - String.begin();
|
|
AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
|
|
Prev = EndPos + 1;
|
|
i = EndPos;
|
|
break;
|
|
}
|
|
|
|
case '.':
|
|
if (InTok)
|
|
AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
|
|
Prev = i;
|
|
InTok = true;
|
|
break;
|
|
|
|
default:
|
|
InTok = true;
|
|
}
|
|
}
|
|
if (InTok && Prev != String.size())
|
|
AsmOperands.push_back(AsmOperand(String.substr(Prev)));
|
|
|
|
// The first token of the instruction is the mnemonic, which must be a
|
|
// simple string, not a $foo variable or a singleton register.
|
|
assert(!AsmOperands.empty() && "Instruction has no tokens?");
|
|
Mnemonic = AsmOperands[0].Token;
|
|
if (Mnemonic[0] == '$' || getSingletonRegisterForAsmOperand(0, Info))
|
|
throw TGError(TheDef->getLoc(),
|
|
"Invalid instruction mnemonic '" + Mnemonic.str() + "'!");
|
|
|
|
// Remove the first operand, it is tracked in the mnemonic field.
|
|
AsmOperands.erase(AsmOperands.begin());
|
|
}
|
|
|
|
bool MatchableInfo::Validate(StringRef CommentDelimiter, bool Hack) const {
|
|
// Reject matchables with no .s string.
|
|
if (AsmString.empty())
|
|
throw TGError(TheDef->getLoc(), "instruction with empty asm string");
|
|
|
|
// Reject any matchables with a newline in them, they should be marked
|
|
// isCodeGenOnly if they are pseudo instructions.
|
|
if (AsmString.find('\n') != std::string::npos)
|
|
throw TGError(TheDef->getLoc(),
|
|
"multiline instruction is not valid for the asmparser, "
|
|
"mark it isCodeGenOnly");
|
|
|
|
// Remove comments from the asm string. We know that the asmstring only
|
|
// has one line.
|
|
if (!CommentDelimiter.empty() &&
|
|
StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
|
|
throw TGError(TheDef->getLoc(),
|
|
"asmstring for instruction has comment character in it, "
|
|
"mark it isCodeGenOnly");
|
|
|
|
// Reject matchables with operand modifiers, these aren't something we can
|
|
// handle, the target should be refactored to use operands instead of
|
|
// modifiers.
|
|
//
|
|
// Also, check for instructions which reference the operand multiple times;
|
|
// this implies a constraint we would not honor.
|
|
std::set<std::string> OperandNames;
|
|
for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
|
|
StringRef Tok = AsmOperands[i].Token;
|
|
if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
|
|
throw TGError(TheDef->getLoc(),
|
|
"matchable with operand modifier '" + Tok.str() +
|
|
"' not supported by asm matcher. Mark isCodeGenOnly!");
|
|
|
|
// Verify that any operand is only mentioned once.
|
|
// We reject aliases and ignore instructions for now.
|
|
if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
|
|
if (!Hack)
|
|
throw TGError(TheDef->getLoc(),
|
|
"ERROR: matchable with tied operand '" + Tok.str() +
|
|
"' can never be matched!");
|
|
// FIXME: Should reject these. The ARM backend hits this with $lane in a
|
|
// bunch of instructions. It is unclear what the right answer is.
|
|
DEBUG({
|
|
errs() << "warning: '" << TheDef->getName() << "': "
|
|
<< "ignoring instruction with tied operand '"
|
|
<< Tok.str() << "'\n";
|
|
});
|
|
return false;
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
/// getSingletonRegisterForAsmOperand - If the specified token is a singleton
|
|
/// register, return the register name, otherwise return a null StringRef.
|
|
Record *MatchableInfo::
|
|
getSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info) const{
|
|
StringRef Tok = AsmOperands[i].Token;
|
|
if (!Tok.startswith(Info.RegisterPrefix))
|
|
return 0;
|
|
|
|
StringRef RegName = Tok.substr(Info.RegisterPrefix.size());
|
|
if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
|
|
return Reg->TheDef;
|
|
|
|
// If there is no register prefix (i.e. "%" in "%eax"), then this may
|
|
// be some random non-register token, just ignore it.
|
|
if (Info.RegisterPrefix.empty())
|
|
return 0;
|
|
|
|
// Otherwise, we have something invalid prefixed with the register prefix,
|
|
// such as %foo.
|
|
std::string Err = "unable to find register for '" + RegName.str() +
|
|
"' (which matches register prefix)";
|
|
throw TGError(TheDef->getLoc(), Err);
|
|
}
|
|
|
|
static std::string getEnumNameForToken(StringRef Str) {
|
|
std::string Res;
|
|
|
|
for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
|
|
switch (*it) {
|
|
case '*': Res += "_STAR_"; break;
|
|
case '%': Res += "_PCT_"; break;
|
|
case ':': Res += "_COLON_"; break;
|
|
case '!': Res += "_EXCLAIM_"; break;
|
|
case '.': Res += "_DOT_"; break;
|
|
default:
|
|
if (isalnum(*it))
|
|
Res += *it;
|
|
else
|
|
Res += "_" + utostr((unsigned) *it) + "_";
|
|
}
|
|
}
|
|
|
|
return Res;
|
|
}
|
|
|
|
ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
|
|
ClassInfo *&Entry = TokenClasses[Token];
|
|
|
|
if (!Entry) {
|
|
Entry = new ClassInfo();
|
|
Entry->Kind = ClassInfo::Token;
|
|
Entry->ClassName = "Token";
|
|
Entry->Name = "MCK_" + getEnumNameForToken(Token);
|
|
Entry->ValueName = Token;
|
|
Entry->PredicateMethod = "<invalid>";
|
|
Entry->RenderMethod = "<invalid>";
|
|
Entry->ParserMethod = "";
|
|
Classes.push_back(Entry);
|
|
}
|
|
|
|
return Entry;
|
|
}
|
|
|
|
ClassInfo *
|
|
AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
|
|
int SubOpIdx) {
|
|
Record *Rec = OI.Rec;
|
|
if (SubOpIdx != -1)
|
|
Rec = dynamic_cast<DefInit*>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
|
|
|
|
if (Rec->isSubClassOf("RegisterOperand")) {
|
|
// RegisterOperand may have an associated ParserMatchClass. If it does,
|
|
// use it, else just fall back to the underlying register class.
|
|
const RecordVal *R = Rec->getValue("ParserMatchClass");
|
|
if (R == 0 || R->getValue() == 0)
|
|
throw "Record `" + Rec->getName() +
|
|
"' does not have a ParserMatchClass!\n";
|
|
|
|
if (DefInit *DI= dynamic_cast<DefInit*>(R->getValue())) {
|
|
Record *MatchClass = DI->getDef();
|
|
if (ClassInfo *CI = AsmOperandClasses[MatchClass])
|
|
return CI;
|
|
}
|
|
|
|
// No custom match class. Just use the register class.
|
|
Record *ClassRec = Rec->getValueAsDef("RegClass");
|
|
if (!ClassRec)
|
|
throw TGError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
|
|
"' has no associated register class!\n");
|
|
if (ClassInfo *CI = RegisterClassClasses[ClassRec])
|
|
return CI;
|
|
throw TGError(Rec->getLoc(), "register class has no class info!");
|
|
}
|
|
|
|
|
|
if (Rec->isSubClassOf("RegisterClass")) {
|
|
if (ClassInfo *CI = RegisterClassClasses[Rec])
|
|
return CI;
|
|
throw TGError(Rec->getLoc(), "register class has no class info!");
|
|
}
|
|
|
|
assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
|
|
Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
|
|
if (ClassInfo *CI = AsmOperandClasses[MatchClass])
|
|
return CI;
|
|
|
|
throw TGError(Rec->getLoc(), "operand has no match class!");
|
|
}
|
|
|
|
void AsmMatcherInfo::
|
|
BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
|
|
const std::vector<CodeGenRegister*> &Registers =
|
|
Target.getRegBank().getRegisters();
|
|
ArrayRef<CodeGenRegisterClass*> RegClassList =
|
|
Target.getRegBank().getRegClasses();
|
|
|
|
// The register sets used for matching.
|
|
std::set< std::set<Record*> > RegisterSets;
|
|
|
|
// Gather the defined sets.
|
|
for (ArrayRef<CodeGenRegisterClass*>::const_iterator it =
|
|
RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it)
|
|
RegisterSets.insert(std::set<Record*>(
|
|
(*it)->getOrder().begin(), (*it)->getOrder().end()));
|
|
|
|
// Add any required singleton sets.
|
|
for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
|
|
ie = SingletonRegisters.end(); it != ie; ++it) {
|
|
Record *Rec = *it;
|
|
RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1));
|
|
}
|
|
|
|
// Introduce derived sets where necessary (when a register does not determine
|
|
// a unique register set class), and build the mapping of registers to the set
|
|
// they should classify to.
|
|
std::map<Record*, std::set<Record*> > RegisterMap;
|
|
for (std::vector<CodeGenRegister*>::const_iterator it = Registers.begin(),
|
|
ie = Registers.end(); it != ie; ++it) {
|
|
const CodeGenRegister &CGR = **it;
|
|
// Compute the intersection of all sets containing this register.
|
|
std::set<Record*> ContainingSet;
|
|
|
|
for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
|
|
ie = RegisterSets.end(); it != ie; ++it) {
|
|
if (!it->count(CGR.TheDef))
|
|
continue;
|
|
|
|
if (ContainingSet.empty()) {
|
|
ContainingSet = *it;
|
|
continue;
|
|
}
|
|
|
|
std::set<Record*> Tmp;
|
|
std::swap(Tmp, ContainingSet);
|
|
std::insert_iterator< std::set<Record*> > II(ContainingSet,
|
|
ContainingSet.begin());
|
|
std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II);
|
|
}
|
|
|
|
if (!ContainingSet.empty()) {
|
|
RegisterSets.insert(ContainingSet);
|
|
RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
|
|
}
|
|
}
|
|
|
|
// Construct the register classes.
|
|
std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses;
|
|
unsigned Index = 0;
|
|
for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
|
|
ie = RegisterSets.end(); it != ie; ++it, ++Index) {
|
|
ClassInfo *CI = new ClassInfo();
|
|
CI->Kind = ClassInfo::RegisterClass0 + Index;
|
|
CI->ClassName = "Reg" + utostr(Index);
|
|
CI->Name = "MCK_Reg" + utostr(Index);
|
|
CI->ValueName = "";
|
|
CI->PredicateMethod = ""; // unused
|
|
CI->RenderMethod = "addRegOperands";
|
|
CI->Registers = *it;
|
|
Classes.push_back(CI);
|
|
RegisterSetClasses.insert(std::make_pair(*it, CI));
|
|
}
|
|
|
|
// Find the superclasses; we could compute only the subgroup lattice edges,
|
|
// but there isn't really a point.
|
|
for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
|
|
ie = RegisterSets.end(); it != ie; ++it) {
|
|
ClassInfo *CI = RegisterSetClasses[*it];
|
|
for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(),
|
|
ie2 = RegisterSets.end(); it2 != ie2; ++it2)
|
|
if (*it != *it2 &&
|
|
std::includes(it2->begin(), it2->end(), it->begin(), it->end()))
|
|
CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
|
|
}
|
|
|
|
// Name the register classes which correspond to a user defined RegisterClass.
|
|
for (ArrayRef<CodeGenRegisterClass*>::const_iterator
|
|
it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) {
|
|
const CodeGenRegisterClass &RC = **it;
|
|
// Def will be NULL for non-user defined register classes.
|
|
Record *Def = RC.getDef();
|
|
if (!Def)
|
|
continue;
|
|
ClassInfo *CI = RegisterSetClasses[std::set<Record*>(RC.getOrder().begin(),
|
|
RC.getOrder().end())];
|
|
if (CI->ValueName.empty()) {
|
|
CI->ClassName = RC.getName();
|
|
CI->Name = "MCK_" + RC.getName();
|
|
CI->ValueName = RC.getName();
|
|
} else
|
|
CI->ValueName = CI->ValueName + "," + RC.getName();
|
|
|
|
RegisterClassClasses.insert(std::make_pair(Def, CI));
|
|
}
|
|
|
|
// Populate the map for individual registers.
|
|
for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(),
|
|
ie = RegisterMap.end(); it != ie; ++it)
|
|
RegisterClasses[it->first] = RegisterSetClasses[it->second];
|
|
|
|
// Name the register classes which correspond to singleton registers.
|
|
for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
|
|
ie = SingletonRegisters.end(); it != ie; ++it) {
|
|
Record *Rec = *it;
|
|
ClassInfo *CI = RegisterClasses[Rec];
|
|
assert(CI && "Missing singleton register class info!");
|
|
|
|
if (CI->ValueName.empty()) {
|
|
CI->ClassName = Rec->getName();
|
|
CI->Name = "MCK_" + Rec->getName();
|
|
CI->ValueName = Rec->getName();
|
|
} else
|
|
CI->ValueName = CI->ValueName + "," + Rec->getName();
|
|
}
|
|
}
|
|
|
|
void AsmMatcherInfo::BuildOperandClasses() {
|
|
std::vector<Record*> AsmOperands =
|
|
Records.getAllDerivedDefinitions("AsmOperandClass");
|
|
|
|
// Pre-populate AsmOperandClasses map.
|
|
for (std::vector<Record*>::iterator it = AsmOperands.begin(),
|
|
ie = AsmOperands.end(); it != ie; ++it)
|
|
AsmOperandClasses[*it] = new ClassInfo();
|
|
|
|
unsigned Index = 0;
|
|
for (std::vector<Record*>::iterator it = AsmOperands.begin(),
|
|
ie = AsmOperands.end(); it != ie; ++it, ++Index) {
|
|
ClassInfo *CI = AsmOperandClasses[*it];
|
|
CI->Kind = ClassInfo::UserClass0 + Index;
|
|
|
|
ListInit *Supers = (*it)->getValueAsListInit("SuperClasses");
|
|
for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
|
|
DefInit *DI = dynamic_cast<DefInit*>(Supers->getElement(i));
|
|
if (!DI) {
|
|
PrintError((*it)->getLoc(), "Invalid super class reference!");
|
|
continue;
|
|
}
|
|
|
|
ClassInfo *SC = AsmOperandClasses[DI->getDef()];
|
|
if (!SC)
|
|
PrintError((*it)->getLoc(), "Invalid super class reference!");
|
|
else
|
|
CI->SuperClasses.push_back(SC);
|
|
}
|
|
CI->ClassName = (*it)->getValueAsString("Name");
|
|
CI->Name = "MCK_" + CI->ClassName;
|
|
CI->ValueName = (*it)->getName();
|
|
|
|
// Get or construct the predicate method name.
|
|
Init *PMName = (*it)->getValueInit("PredicateMethod");
|
|
if (StringInit *SI = dynamic_cast<StringInit*>(PMName)) {
|
|
CI->PredicateMethod = SI->getValue();
|
|
} else {
|
|
assert(dynamic_cast<UnsetInit*>(PMName) &&
|
|
"Unexpected PredicateMethod field!");
|
|
CI->PredicateMethod = "is" + CI->ClassName;
|
|
}
|
|
|
|
// Get or construct the render method name.
|
|
Init *RMName = (*it)->getValueInit("RenderMethod");
|
|
if (StringInit *SI = dynamic_cast<StringInit*>(RMName)) {
|
|
CI->RenderMethod = SI->getValue();
|
|
} else {
|
|
assert(dynamic_cast<UnsetInit*>(RMName) &&
|
|
"Unexpected RenderMethod field!");
|
|
CI->RenderMethod = "add" + CI->ClassName + "Operands";
|
|
}
|
|
|
|
// Get the parse method name or leave it as empty.
|
|
Init *PRMName = (*it)->getValueInit("ParserMethod");
|
|
if (StringInit *SI = dynamic_cast<StringInit*>(PRMName))
|
|
CI->ParserMethod = SI->getValue();
|
|
|
|
AsmOperandClasses[*it] = CI;
|
|
Classes.push_back(CI);
|
|
}
|
|
}
|
|
|
|
AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
|
|
CodeGenTarget &target,
|
|
RecordKeeper &records)
|
|
: Records(records), AsmParser(asmParser), Target(target),
|
|
RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix")) {
|
|
}
|
|
|
|
/// BuildOperandMatchInfo - Build the necessary information to handle user
|
|
/// defined operand parsing methods.
|
|
void AsmMatcherInfo::BuildOperandMatchInfo() {
|
|
|
|
/// Map containing a mask with all operands indicies that can be found for
|
|
/// that class inside a instruction.
|
|
std::map<ClassInfo*, unsigned> OpClassMask;
|
|
|
|
for (std::vector<MatchableInfo*>::const_iterator it =
|
|
Matchables.begin(), ie = Matchables.end();
|
|
it != ie; ++it) {
|
|
MatchableInfo &II = **it;
|
|
OpClassMask.clear();
|
|
|
|
// Keep track of all operands of this instructions which belong to the
|
|
// same class.
|
|
for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
|
|
MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
|
|
if (Op.Class->ParserMethod.empty())
|
|
continue;
|
|
unsigned &OperandMask = OpClassMask[Op.Class];
|
|
OperandMask |= (1 << i);
|
|
}
|
|
|
|
// Generate operand match info for each mnemonic/operand class pair.
|
|
for (std::map<ClassInfo*, unsigned>::iterator iit = OpClassMask.begin(),
|
|
iie = OpClassMask.end(); iit != iie; ++iit) {
|
|
unsigned OpMask = iit->second;
|
|
ClassInfo *CI = iit->first;
|
|
OperandMatchInfo.push_back(OperandMatchEntry::Create(&II, CI, OpMask));
|
|
}
|
|
}
|
|
}
|
|
|
|
void AsmMatcherInfo::BuildInfo() {
|
|
// Build information about all of the AssemblerPredicates.
|
|
std::vector<Record*> AllPredicates =
|
|
Records.getAllDerivedDefinitions("Predicate");
|
|
for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
|
|
Record *Pred = AllPredicates[i];
|
|
// Ignore predicates that are not intended for the assembler.
|
|
if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
|
|
continue;
|
|
|
|
if (Pred->getName().empty())
|
|
throw TGError(Pred->getLoc(), "Predicate has no name!");
|
|
|
|
unsigned FeatureNo = SubtargetFeatures.size();
|
|
SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
|
|
assert(FeatureNo < 32 && "Too many subtarget features!");
|
|
}
|
|
|
|
std::string CommentDelimiter = AsmParser->getValueAsString("CommentDelimiter");
|
|
|
|
// Parse the instructions; we need to do this first so that we can gather the
|
|
// singleton register classes.
|
|
SmallPtrSet<Record*, 16> SingletonRegisters;
|
|
for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
|
|
E = Target.inst_end(); I != E; ++I) {
|
|
const CodeGenInstruction &CGI = **I;
|
|
|
|
// If the tblgen -match-prefix option is specified (for tblgen hackers),
|
|
// filter the set of instructions we consider.
|
|
if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
|
|
continue;
|
|
|
|
// Ignore "codegen only" instructions.
|
|
if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
|
|
continue;
|
|
|
|
// Validate the operand list to ensure we can handle this instruction.
|
|
for (unsigned i = 0, e = CGI.Operands.size(); i != e; ++i) {
|
|
const CGIOperandList::OperandInfo &OI = CGI.Operands[i];
|
|
|
|
// Validate tied operands.
|
|
if (OI.getTiedRegister() != -1) {
|
|
// If we have a tied operand that consists of multiple MCOperands,
|
|
// reject it. We reject aliases and ignore instructions for now.
|
|
if (OI.MINumOperands != 1) {
|
|
// FIXME: Should reject these. The ARM backend hits this with $lane
|
|
// in a bunch of instructions. It is unclear what the right answer is.
|
|
DEBUG({
|
|
errs() << "warning: '" << CGI.TheDef->getName() << "': "
|
|
<< "ignoring instruction with multi-operand tied operand '"
|
|
<< OI.Name << "'\n";
|
|
});
|
|
continue;
|
|
}
|
|
}
|
|
}
|
|
|
|
OwningPtr<MatchableInfo> II(new MatchableInfo(CGI));
|
|
|
|
II->Initialize(*this, SingletonRegisters);
|
|
|
|
// Ignore instructions which shouldn't be matched and diagnose invalid
|
|
// instruction definitions with an error.
|
|
if (!II->Validate(CommentDelimiter, true))
|
|
continue;
|
|
|
|
// Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
|
|
//
|
|
// FIXME: This is a total hack.
|
|
if (StringRef(II->TheDef->getName()).startswith("Int_") ||
|
|
StringRef(II->TheDef->getName()).endswith("_Int"))
|
|
continue;
|
|
|
|
Matchables.push_back(II.take());
|
|
}
|
|
|
|
// Parse all of the InstAlias definitions and stick them in the list of
|
|
// matchables.
|
|
std::vector<Record*> AllInstAliases =
|
|
Records.getAllDerivedDefinitions("InstAlias");
|
|
for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
|
|
CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i], Target);
|
|
|
|
// If the tblgen -match-prefix option is specified (for tblgen hackers),
|
|
// filter the set of instruction aliases we consider, based on the target
|
|
// instruction.
|
|
if (!StringRef(Alias->ResultInst->TheDef->getName()).startswith(
|
|
MatchPrefix))
|
|
continue;
|
|
|
|
OwningPtr<MatchableInfo> II(new MatchableInfo(Alias));
|
|
|
|
II->Initialize(*this, SingletonRegisters);
|
|
|
|
// Validate the alias definitions.
|
|
II->Validate(CommentDelimiter, false);
|
|
|
|
Matchables.push_back(II.take());
|
|
}
|
|
|
|
// Build info for the register classes.
|
|
BuildRegisterClasses(SingletonRegisters);
|
|
|
|
// Build info for the user defined assembly operand classes.
|
|
BuildOperandClasses();
|
|
|
|
// Build the information about matchables, now that we have fully formed
|
|
// classes.
|
|
for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(),
|
|
ie = Matchables.end(); it != ie; ++it) {
|
|
MatchableInfo *II = *it;
|
|
|
|
// Parse the tokens after the mnemonic.
|
|
// Note: BuildInstructionOperandReference may insert new AsmOperands, so
|
|
// don't precompute the loop bound.
|
|
for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
|
|
MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
|
|
StringRef Token = Op.Token;
|
|
|
|
// Check for singleton registers.
|
|
if (Record *RegRecord = II->getSingletonRegisterForAsmOperand(i, *this)) {
|
|
Op.Class = RegisterClasses[RegRecord];
|
|
assert(Op.Class && Op.Class->Registers.size() == 1 &&
|
|
"Unexpected class for singleton register");
|
|
continue;
|
|
}
|
|
|
|
// Check for simple tokens.
|
|
if (Token[0] != '$') {
|
|
Op.Class = getTokenClass(Token);
|
|
continue;
|
|
}
|
|
|
|
if (Token.size() > 1 && isdigit(Token[1])) {
|
|
Op.Class = getTokenClass(Token);
|
|
continue;
|
|
}
|
|
|
|
// Otherwise this is an operand reference.
|
|
StringRef OperandName;
|
|
if (Token[1] == '{')
|
|
OperandName = Token.substr(2, Token.size() - 3);
|
|
else
|
|
OperandName = Token.substr(1);
|
|
|
|
if (II->DefRec.is<const CodeGenInstruction*>())
|
|
BuildInstructionOperandReference(II, OperandName, i);
|
|
else
|
|
BuildAliasOperandReference(II, OperandName, Op);
|
|
}
|
|
|
|
if (II->DefRec.is<const CodeGenInstruction*>())
|
|
II->BuildInstructionResultOperands();
|
|
else
|
|
II->BuildAliasResultOperands();
|
|
}
|
|
|
|
// Reorder classes so that classes precede super classes.
|
|
std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
|
|
}
|
|
|
|
/// BuildInstructionOperandReference - The specified operand is a reference to a
|
|
/// named operand such as $src. Resolve the Class and OperandInfo pointers.
|
|
void AsmMatcherInfo::
|
|
BuildInstructionOperandReference(MatchableInfo *II,
|
|
StringRef OperandName,
|
|
unsigned AsmOpIdx) {
|
|
const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
|
|
const CGIOperandList &Operands = CGI.Operands;
|
|
MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
|
|
|
|
// Map this token to an operand.
|
|
unsigned Idx;
|
|
if (!Operands.hasOperandNamed(OperandName, Idx))
|
|
throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
|
|
OperandName.str() + "'");
|
|
|
|
// If the instruction operand has multiple suboperands, but the parser
|
|
// match class for the asm operand is still the default "ImmAsmOperand",
|
|
// then handle each suboperand separately.
|
|
if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
|
|
Record *Rec = Operands[Idx].Rec;
|
|
assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
|
|
Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
|
|
if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
|
|
// Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
|
|
StringRef Token = Op->Token; // save this in case Op gets moved
|
|
for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
|
|
MatchableInfo::AsmOperand NewAsmOp(Token);
|
|
NewAsmOp.SubOpIdx = SI;
|
|
II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
|
|
}
|
|
// Replace Op with first suboperand.
|
|
Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
|
|
Op->SubOpIdx = 0;
|
|
}
|
|
}
|
|
|
|
// Set up the operand class.
|
|
Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
|
|
|
|
// If the named operand is tied, canonicalize it to the untied operand.
|
|
// For example, something like:
|
|
// (outs GPR:$dst), (ins GPR:$src)
|
|
// with an asmstring of
|
|
// "inc $src"
|
|
// we want to canonicalize to:
|
|
// "inc $dst"
|
|
// so that we know how to provide the $dst operand when filling in the result.
|
|
int OITied = Operands[Idx].getTiedRegister();
|
|
if (OITied != -1) {
|
|
// The tied operand index is an MIOperand index, find the operand that
|
|
// contains it.
|
|
std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
|
|
OperandName = Operands[Idx.first].Name;
|
|
Op->SubOpIdx = Idx.second;
|
|
}
|
|
|
|
Op->SrcOpName = OperandName;
|
|
}
|
|
|
|
/// BuildAliasOperandReference - When parsing an operand reference out of the
|
|
/// matching string (e.g. "movsx $src, $dst"), determine what the class of the
|
|
/// operand reference is by looking it up in the result pattern definition.
|
|
void AsmMatcherInfo::BuildAliasOperandReference(MatchableInfo *II,
|
|
StringRef OperandName,
|
|
MatchableInfo::AsmOperand &Op) {
|
|
const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
|
|
|
|
// Set up the operand class.
|
|
for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
|
|
if (CGA.ResultOperands[i].isRecord() &&
|
|
CGA.ResultOperands[i].getName() == OperandName) {
|
|
// It's safe to go with the first one we find, because CodeGenInstAlias
|
|
// validates that all operands with the same name have the same record.
|
|
unsigned ResultIdx = CGA.ResultInstOperandIndex[i].first;
|
|
Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
|
|
Op.Class = getOperandClass(CGA.ResultInst->Operands[ResultIdx],
|
|
Op.SubOpIdx);
|
|
Op.SrcOpName = OperandName;
|
|
return;
|
|
}
|
|
|
|
throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
|
|
OperandName.str() + "'");
|
|
}
|
|
|
|
void MatchableInfo::BuildInstructionResultOperands() {
|
|
const CodeGenInstruction *ResultInst = getResultInst();
|
|
|
|
// Loop over all operands of the result instruction, determining how to
|
|
// populate them.
|
|
for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
|
|
const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
|
|
|
|
// If this is a tied operand, just copy from the previously handled operand.
|
|
int TiedOp = OpInfo.getTiedRegister();
|
|
if (TiedOp != -1) {
|
|
ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
|
|
continue;
|
|
}
|
|
|
|
// Find out what operand from the asmparser this MCInst operand comes from.
|
|
int SrcOperand = FindAsmOperandNamed(OpInfo.Name);
|
|
if (OpInfo.Name.empty() || SrcOperand == -1)
|
|
throw TGError(TheDef->getLoc(), "Instruction '" +
|
|
TheDef->getName() + "' has operand '" + OpInfo.Name +
|
|
"' that doesn't appear in asm string!");
|
|
|
|
// Check if the one AsmOperand populates the entire operand.
|
|
unsigned NumOperands = OpInfo.MINumOperands;
|
|
if (AsmOperands[SrcOperand].SubOpIdx == -1) {
|
|
ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
|
|
continue;
|
|
}
|
|
|
|
// Add a separate ResOperand for each suboperand.
|
|
for (unsigned AI = 0; AI < NumOperands; ++AI) {
|
|
assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
|
|
AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
|
|
"unexpected AsmOperands for suboperands");
|
|
ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
|
|
}
|
|
}
|
|
}
|
|
|
|
void MatchableInfo::BuildAliasResultOperands() {
|
|
const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
|
|
const CodeGenInstruction *ResultInst = getResultInst();
|
|
|
|
// Loop over all operands of the result instruction, determining how to
|
|
// populate them.
|
|
unsigned AliasOpNo = 0;
|
|
unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
|
|
for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
|
|
const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
|
|
|
|
// If this is a tied operand, just copy from the previously handled operand.
|
|
int TiedOp = OpInfo->getTiedRegister();
|
|
if (TiedOp != -1) {
|
|
ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
|
|
continue;
|
|
}
|
|
|
|
// Handle all the suboperands for this operand.
|
|
const std::string &OpName = OpInfo->Name;
|
|
for ( ; AliasOpNo < LastOpNo &&
|
|
CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
|
|
int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
|
|
|
|
// Find out what operand from the asmparser that this MCInst operand
|
|
// comes from.
|
|
switch (CGA.ResultOperands[AliasOpNo].Kind) {
|
|
default: assert(0 && "unexpected InstAlias operand kind");
|
|
case CodeGenInstAlias::ResultOperand::K_Record: {
|
|
StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
|
|
int SrcOperand = FindAsmOperand(Name, SubIdx);
|
|
if (SrcOperand == -1)
|
|
throw TGError(TheDef->getLoc(), "Instruction '" +
|
|
TheDef->getName() + "' has operand '" + OpName +
|
|
"' that doesn't appear in asm string!");
|
|
unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
|
|
ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
|
|
NumOperands));
|
|
break;
|
|
}
|
|
case CodeGenInstAlias::ResultOperand::K_Imm: {
|
|
int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
|
|
ResOperands.push_back(ResOperand::getImmOp(ImmVal));
|
|
break;
|
|
}
|
|
case CodeGenInstAlias::ResultOperand::K_Reg: {
|
|
Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
|
|
ResOperands.push_back(ResOperand::getRegOp(Reg));
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
static void EmitConvertToMCInst(CodeGenTarget &Target, StringRef ClassName,
|
|
std::vector<MatchableInfo*> &Infos,
|
|
raw_ostream &OS) {
|
|
// Write the convert function to a separate stream, so we can drop it after
|
|
// the enum.
|
|
std::string ConvertFnBody;
|
|
raw_string_ostream CvtOS(ConvertFnBody);
|
|
|
|
// Function we have already generated.
|
|
std::set<std::string> GeneratedFns;
|
|
|
|
// Start the unified conversion function.
|
|
CvtOS << "bool " << Target.getName() << ClassName << "::\n";
|
|
CvtOS << "ConvertToMCInst(unsigned Kind, MCInst &Inst, "
|
|
<< "unsigned Opcode,\n"
|
|
<< " const SmallVectorImpl<MCParsedAsmOperand*"
|
|
<< "> &Operands) {\n";
|
|
CvtOS << " Inst.setOpcode(Opcode);\n";
|
|
CvtOS << " switch (Kind) {\n";
|
|
CvtOS << " default:\n";
|
|
|
|
// Start the enum, which we will generate inline.
|
|
|
|
OS << "// Unified function for converting operands to MCInst instances.\n\n";
|
|
OS << "enum ConversionKind {\n";
|
|
|
|
// TargetOperandClass - This is the target's operand class, like X86Operand.
|
|
std::string TargetOperandClass = Target.getName() + "Operand";
|
|
|
|
for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(),
|
|
ie = Infos.end(); it != ie; ++it) {
|
|
MatchableInfo &II = **it;
|
|
|
|
// Check if we have a custom match function.
|
|
std::string AsmMatchConverter =
|
|
II.getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
|
|
if (!AsmMatchConverter.empty()) {
|
|
std::string Signature = "ConvertCustom_" + AsmMatchConverter;
|
|
II.ConversionFnKind = Signature;
|
|
|
|
// Check if we have already generated this signature.
|
|
if (!GeneratedFns.insert(Signature).second)
|
|
continue;
|
|
|
|
// If not, emit it now. Add to the enum list.
|
|
OS << " " << Signature << ",\n";
|
|
|
|
CvtOS << " case " << Signature << ":\n";
|
|
CvtOS << " return " << AsmMatchConverter
|
|
<< "(Inst, Opcode, Operands);\n";
|
|
continue;
|
|
}
|
|
|
|
// Build the conversion function signature.
|
|
std::string Signature = "Convert";
|
|
std::string CaseBody;
|
|
raw_string_ostream CaseOS(CaseBody);
|
|
|
|
// Compute the convert enum and the case body.
|
|
for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) {
|
|
const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i];
|
|
|
|
// Generate code to populate each result operand.
|
|
switch (OpInfo.Kind) {
|
|
case MatchableInfo::ResOperand::RenderAsmOperand: {
|
|
// This comes from something we parsed.
|
|
MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum];
|
|
|
|
// Registers are always converted the same, don't duplicate the
|
|
// conversion function based on them.
|
|
Signature += "__";
|
|
if (Op.Class->isRegisterClass())
|
|
Signature += "Reg";
|
|
else
|
|
Signature += Op.Class->ClassName;
|
|
Signature += utostr(OpInfo.MINumOperands);
|
|
Signature += "_" + itostr(OpInfo.AsmOperandNum);
|
|
|
|
CaseOS << " ((" << TargetOperandClass << "*)Operands["
|
|
<< (OpInfo.AsmOperandNum+1) << "])->" << Op.Class->RenderMethod
|
|
<< "(Inst, " << OpInfo.MINumOperands << ");\n";
|
|
break;
|
|
}
|
|
|
|
case MatchableInfo::ResOperand::TiedOperand: {
|
|
// If this operand is tied to a previous one, just copy the MCInst
|
|
// operand from the earlier one.We can only tie single MCOperand values.
|
|
//assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
|
|
unsigned TiedOp = OpInfo.TiedOperandNum;
|
|
assert(i > TiedOp && "Tied operand precedes its target!");
|
|
CaseOS << " Inst.addOperand(Inst.getOperand(" << TiedOp << "));\n";
|
|
Signature += "__Tie" + utostr(TiedOp);
|
|
break;
|
|
}
|
|
case MatchableInfo::ResOperand::ImmOperand: {
|
|
int64_t Val = OpInfo.ImmVal;
|
|
CaseOS << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n";
|
|
Signature += "__imm" + itostr(Val);
|
|
break;
|
|
}
|
|
case MatchableInfo::ResOperand::RegOperand: {
|
|
if (OpInfo.Register == 0) {
|
|
CaseOS << " Inst.addOperand(MCOperand::CreateReg(0));\n";
|
|
Signature += "__reg0";
|
|
} else {
|
|
std::string N = getQualifiedName(OpInfo.Register);
|
|
CaseOS << " Inst.addOperand(MCOperand::CreateReg(" << N << "));\n";
|
|
Signature += "__reg" + OpInfo.Register->getName();
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
II.ConversionFnKind = Signature;
|
|
|
|
// Check if we have already generated this signature.
|
|
if (!GeneratedFns.insert(Signature).second)
|
|
continue;
|
|
|
|
// If not, emit it now. Add to the enum list.
|
|
OS << " " << Signature << ",\n";
|
|
|
|
CvtOS << " case " << Signature << ":\n";
|
|
CvtOS << CaseOS.str();
|
|
CvtOS << " return true;\n";
|
|
}
|
|
|
|
// Finish the convert function.
|
|
|
|
CvtOS << " }\n";
|
|
CvtOS << " return false;\n";
|
|
CvtOS << "}\n\n";
|
|
|
|
// Finish the enum, and drop the convert function after it.
|
|
|
|
OS << " NumConversionVariants\n";
|
|
OS << "};\n\n";
|
|
|
|
OS << CvtOS.str();
|
|
}
|
|
|
|
/// EmitMatchClassEnumeration - Emit the enumeration for match class kinds.
|
|
static void EmitMatchClassEnumeration(CodeGenTarget &Target,
|
|
std::vector<ClassInfo*> &Infos,
|
|
raw_ostream &OS) {
|
|
OS << "namespace {\n\n";
|
|
|
|
OS << "/// MatchClassKind - The kinds of classes which participate in\n"
|
|
<< "/// instruction matching.\n";
|
|
OS << "enum MatchClassKind {\n";
|
|
OS << " InvalidMatchClass = 0,\n";
|
|
for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
|
|
ie = Infos.end(); it != ie; ++it) {
|
|
ClassInfo &CI = **it;
|
|
OS << " " << CI.Name << ", // ";
|
|
if (CI.Kind == ClassInfo::Token) {
|
|
OS << "'" << CI.ValueName << "'\n";
|
|
} else if (CI.isRegisterClass()) {
|
|
if (!CI.ValueName.empty())
|
|
OS << "register class '" << CI.ValueName << "'\n";
|
|
else
|
|
OS << "derived register class\n";
|
|
} else {
|
|
OS << "user defined class '" << CI.ValueName << "'\n";
|
|
}
|
|
}
|
|
OS << " NumMatchClassKinds\n";
|
|
OS << "};\n\n";
|
|
|
|
OS << "}\n\n";
|
|
}
|
|
|
|
/// EmitValidateOperandClass - Emit the function to validate an operand class.
|
|
static void EmitValidateOperandClass(AsmMatcherInfo &Info,
|
|
raw_ostream &OS) {
|
|
OS << "static bool ValidateOperandClass(MCParsedAsmOperand *GOp, "
|
|
<< "MatchClassKind Kind) {\n";
|
|
OS << " " << Info.Target.getName() << "Operand &Operand = *("
|
|
<< Info.Target.getName() << "Operand*)GOp;\n";
|
|
|
|
// The InvalidMatchClass is not to match any operand.
|
|
OS << " if (Kind == InvalidMatchClass)\n";
|
|
OS << " return false;\n\n";
|
|
|
|
// Check for Token operands first.
|
|
OS << " if (Operand.isToken())\n";
|
|
OS << " return MatchTokenString(Operand.getToken()) == Kind;\n\n";
|
|
|
|
// Check for register operands, including sub-classes.
|
|
OS << " if (Operand.isReg()) {\n";
|
|
OS << " MatchClassKind OpKind;\n";
|
|
OS << " switch (Operand.getReg()) {\n";
|
|
OS << " default: OpKind = InvalidMatchClass; break;\n";
|
|
for (std::map<Record*, ClassInfo*>::iterator
|
|
it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
|
|
it != ie; ++it)
|
|
OS << " case " << Info.Target.getName() << "::"
|
|
<< it->first->getName() << ": OpKind = " << it->second->Name
|
|
<< "; break;\n";
|
|
OS << " }\n";
|
|
OS << " return IsSubclass(OpKind, Kind);\n";
|
|
OS << " }\n\n";
|
|
|
|
// Check the user classes. We don't care what order since we're only
|
|
// actually matching against one of them.
|
|
for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
|
|
ie = Info.Classes.end(); it != ie; ++it) {
|
|
ClassInfo &CI = **it;
|
|
|
|
if (!CI.isUserClass())
|
|
continue;
|
|
|
|
OS << " // '" << CI.ClassName << "' class\n";
|
|
OS << " if (Kind == " << CI.Name
|
|
<< " && Operand." << CI.PredicateMethod << "()) {\n";
|
|
OS << " return true;\n";
|
|
OS << " }\n\n";
|
|
}
|
|
|
|
OS << " return false;\n";
|
|
OS << "}\n\n";
|
|
}
|
|
|
|
/// EmitIsSubclass - Emit the subclass predicate function.
|
|
static void EmitIsSubclass(CodeGenTarget &Target,
|
|
std::vector<ClassInfo*> &Infos,
|
|
raw_ostream &OS) {
|
|
OS << "/// IsSubclass - Compute whether \\arg A is a subclass of \\arg B.\n";
|
|
OS << "static bool IsSubclass(MatchClassKind A, MatchClassKind B) {\n";
|
|
OS << " if (A == B)\n";
|
|
OS << " return true;\n\n";
|
|
|
|
OS << " switch (A) {\n";
|
|
OS << " default:\n";
|
|
OS << " return false;\n";
|
|
for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
|
|
ie = Infos.end(); it != ie; ++it) {
|
|
ClassInfo &A = **it;
|
|
|
|
if (A.Kind != ClassInfo::Token) {
|
|
std::vector<StringRef> SuperClasses;
|
|
for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
|
|
ie = Infos.end(); it != ie; ++it) {
|
|
ClassInfo &B = **it;
|
|
|
|
if (&A != &B && A.isSubsetOf(B))
|
|
SuperClasses.push_back(B.Name);
|
|
}
|
|
|
|
if (SuperClasses.empty())
|
|
continue;
|
|
|
|
OS << "\n case " << A.Name << ":\n";
|
|
|
|
if (SuperClasses.size() == 1) {
|
|
OS << " return B == " << SuperClasses.back() << ";\n";
|
|
continue;
|
|
}
|
|
|
|
OS << " switch (B) {\n";
|
|
OS << " default: return false;\n";
|
|
for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
|
|
OS << " case " << SuperClasses[i] << ": return true;\n";
|
|
OS << " }\n";
|
|
}
|
|
}
|
|
OS << " }\n";
|
|
OS << "}\n\n";
|
|
}
|
|
|
|
/// EmitMatchTokenString - Emit the function to match a token string to the
|
|
/// appropriate match class value.
|
|
static void EmitMatchTokenString(CodeGenTarget &Target,
|
|
std::vector<ClassInfo*> &Infos,
|
|
raw_ostream &OS) {
|
|
// Construct the match list.
|
|
std::vector<StringMatcher::StringPair> Matches;
|
|
for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
|
|
ie = Infos.end(); it != ie; ++it) {
|
|
ClassInfo &CI = **it;
|
|
|
|
if (CI.Kind == ClassInfo::Token)
|
|
Matches.push_back(StringMatcher::StringPair(CI.ValueName,
|
|
"return " + CI.Name + ";"));
|
|
}
|
|
|
|
OS << "static MatchClassKind MatchTokenString(StringRef Name) {\n";
|
|
|
|
StringMatcher("Name", Matches, OS).Emit();
|
|
|
|
OS << " return InvalidMatchClass;\n";
|
|
OS << "}\n\n";
|
|
}
|
|
|
|
/// EmitMatchRegisterName - Emit the function to match a string to the target
|
|
/// specific register enum.
|
|
static void EmitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
|
|
raw_ostream &OS) {
|
|
// Construct the match list.
|
|
std::vector<StringMatcher::StringPair> Matches;
|
|
const std::vector<CodeGenRegister*> &Regs =
|
|
Target.getRegBank().getRegisters();
|
|
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
|
|
const CodeGenRegister *Reg = Regs[i];
|
|
if (Reg->TheDef->getValueAsString("AsmName").empty())
|
|
continue;
|
|
|
|
Matches.push_back(StringMatcher::StringPair(
|
|
Reg->TheDef->getValueAsString("AsmName"),
|
|
"return " + utostr(Reg->EnumValue) + ";"));
|
|
}
|
|
|
|
OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
|
|
|
|
StringMatcher("Name", Matches, OS).Emit();
|
|
|
|
OS << " return 0;\n";
|
|
OS << "}\n\n";
|
|
}
|
|
|
|
/// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
|
|
/// definitions.
|
|
static void EmitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
|
|
raw_ostream &OS) {
|
|
OS << "// Flags for subtarget features that participate in "
|
|
<< "instruction matching.\n";
|
|
OS << "enum SubtargetFeatureFlag {\n";
|
|
for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
|
|
it = Info.SubtargetFeatures.begin(),
|
|
ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
|
|
SubtargetFeatureInfo &SFI = *it->second;
|
|
OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
|
|
}
|
|
OS << " Feature_None = 0\n";
|
|
OS << "};\n\n";
|
|
}
|
|
|
|
/// EmitComputeAvailableFeatures - Emit the function to compute the list of
|
|
/// available features given a subtarget.
|
|
static void EmitComputeAvailableFeatures(AsmMatcherInfo &Info,
|
|
raw_ostream &OS) {
|
|
std::string ClassName =
|
|
Info.AsmParser->getValueAsString("AsmParserClassName");
|
|
|
|
OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
|
|
<< "ComputeAvailableFeatures(uint64_t FB) const {\n";
|
|
OS << " unsigned Features = 0;\n";
|
|
for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
|
|
it = Info.SubtargetFeatures.begin(),
|
|
ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
|
|
SubtargetFeatureInfo &SFI = *it->second;
|
|
|
|
OS << " if (";
|
|
std::string CondStorage = SFI.TheDef->getValueAsString("AssemblerCondString");
|
|
StringRef Conds = CondStorage;
|
|
std::pair<StringRef,StringRef> Comma = Conds.split(',');
|
|
bool First = true;
|
|
do {
|
|
if (!First)
|
|
OS << " && ";
|
|
|
|
bool Neg = false;
|
|
StringRef Cond = Comma.first;
|
|
if (Cond[0] == '!') {
|
|
Neg = true;
|
|
Cond = Cond.substr(1);
|
|
}
|
|
|
|
OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")";
|
|
if (Neg)
|
|
OS << " == 0";
|
|
else
|
|
OS << " != 0";
|
|
OS << ")";
|
|
|
|
if (Comma.second.empty())
|
|
break;
|
|
|
|
First = false;
|
|
Comma = Comma.second.split(',');
|
|
} while (true);
|
|
|
|
OS << ")\n";
|
|
OS << " Features |= " << SFI.getEnumName() << ";\n";
|
|
}
|
|
OS << " return Features;\n";
|
|
OS << "}\n\n";
|
|
}
|
|
|
|
static std::string GetAliasRequiredFeatures(Record *R,
|
|
const AsmMatcherInfo &Info) {
|
|
std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
|
|
std::string Result;
|
|
unsigned NumFeatures = 0;
|
|
for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
|
|
SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
|
|
|
|
if (F == 0)
|
|
throw TGError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
|
|
"' is not marked as an AssemblerPredicate!");
|
|
|
|
if (NumFeatures)
|
|
Result += '|';
|
|
|
|
Result += F->getEnumName();
|
|
++NumFeatures;
|
|
}
|
|
|
|
if (NumFeatures > 1)
|
|
Result = '(' + Result + ')';
|
|
return Result;
|
|
}
|
|
|
|
/// EmitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
|
|
/// emit a function for them and return true, otherwise return false.
|
|
static bool EmitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) {
|
|
// Ignore aliases when match-prefix is set.
|
|
if (!MatchPrefix.empty())
|
|
return false;
|
|
|
|
std::vector<Record*> Aliases =
|
|
Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
|
|
if (Aliases.empty()) return false;
|
|
|
|
OS << "static void ApplyMnemonicAliases(StringRef &Mnemonic, "
|
|
"unsigned Features) {\n";
|
|
|
|
// Keep track of all the aliases from a mnemonic. Use an std::map so that the
|
|
// iteration order of the map is stable.
|
|
std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
|
|
|
|
for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
|
|
Record *R = Aliases[i];
|
|
AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
|
|
}
|
|
|
|
// Process each alias a "from" mnemonic at a time, building the code executed
|
|
// by the string remapper.
|
|
std::vector<StringMatcher::StringPair> Cases;
|
|
for (std::map<std::string, std::vector<Record*> >::iterator
|
|
I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
|
|
I != E; ++I) {
|
|
const std::vector<Record*> &ToVec = I->second;
|
|
|
|
// Loop through each alias and emit code that handles each case. If there
|
|
// are two instructions without predicates, emit an error. If there is one,
|
|
// emit it last.
|
|
std::string MatchCode;
|
|
int AliasWithNoPredicate = -1;
|
|
|
|
for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
|
|
Record *R = ToVec[i];
|
|
std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
|
|
|
|
// If this unconditionally matches, remember it for later and diagnose
|
|
// duplicates.
|
|
if (FeatureMask.empty()) {
|
|
if (AliasWithNoPredicate != -1) {
|
|
// We can't have two aliases from the same mnemonic with no predicate.
|
|
PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
|
|
"two MnemonicAliases with the same 'from' mnemonic!");
|
|
throw TGError(R->getLoc(), "this is the other MnemonicAlias.");
|
|
}
|
|
|
|
AliasWithNoPredicate = i;
|
|
continue;
|
|
}
|
|
if (R->getValueAsString("ToMnemonic") == I->first)
|
|
throw TGError(R->getLoc(), "MnemonicAlias to the same string");
|
|
|
|
if (!MatchCode.empty())
|
|
MatchCode += "else ";
|
|
MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
|
|
MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
|
|
}
|
|
|
|
if (AliasWithNoPredicate != -1) {
|
|
Record *R = ToVec[AliasWithNoPredicate];
|
|
if (!MatchCode.empty())
|
|
MatchCode += "else\n ";
|
|
MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
|
|
}
|
|
|
|
MatchCode += "return;";
|
|
|
|
Cases.push_back(std::make_pair(I->first, MatchCode));
|
|
}
|
|
|
|
StringMatcher("Mnemonic", Cases, OS).Emit();
|
|
OS << "}\n\n";
|
|
|
|
return true;
|
|
}
|
|
|
|
static const char *getMinimalTypeForRange(uint64_t Range) {
|
|
assert(Range < 0xFFFFFFFFULL && "Enum too large");
|
|
if (Range > 0xFFFF)
|
|
return "uint32_t";
|
|
if (Range > 0xFF)
|
|
return "uint16_t";
|
|
return "uint8_t";
|
|
}
|
|
|
|
static void EmitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
|
|
const AsmMatcherInfo &Info, StringRef ClassName) {
|
|
// Emit the static custom operand parsing table;
|
|
OS << "namespace {\n";
|
|
OS << " struct OperandMatchEntry {\n";
|
|
OS << " const char *Mnemonic;\n";
|
|
OS << " unsigned OperandMask;\n";
|
|
OS << " MatchClassKind Class;\n";
|
|
OS << " unsigned RequiredFeatures;\n";
|
|
OS << " };\n\n";
|
|
|
|
OS << " // Predicate for searching for an opcode.\n";
|
|
OS << " struct LessOpcodeOperand {\n";
|
|
OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
|
|
OS << " return StringRef(LHS.Mnemonic) < RHS;\n";
|
|
OS << " }\n";
|
|
OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
|
|
OS << " return LHS < StringRef(RHS.Mnemonic);\n";
|
|
OS << " }\n";
|
|
OS << " bool operator()(const OperandMatchEntry &LHS,";
|
|
OS << " const OperandMatchEntry &RHS) {\n";
|
|
OS << " return StringRef(LHS.Mnemonic) < StringRef(RHS.Mnemonic);\n";
|
|
OS << " }\n";
|
|
OS << " };\n";
|
|
|
|
OS << "} // end anonymous namespace.\n\n";
|
|
|
|
OS << "static const OperandMatchEntry OperandMatchTable["
|
|
<< Info.OperandMatchInfo.size() << "] = {\n";
|
|
|
|
OS << " /* Mnemonic, Operand List Mask, Operand Class, Features */\n";
|
|
for (std::vector<OperandMatchEntry>::const_iterator it =
|
|
Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
|
|
it != ie; ++it) {
|
|
const OperandMatchEntry &OMI = *it;
|
|
const MatchableInfo &II = *OMI.MI;
|
|
|
|
OS << " { \"" << II.Mnemonic << "\""
|
|
<< ", " << OMI.OperandMask;
|
|
|
|
OS << " /* ";
|
|
bool printComma = false;
|
|
for (int i = 0, e = 31; i !=e; ++i)
|
|
if (OMI.OperandMask & (1 << i)) {
|
|
if (printComma)
|
|
OS << ", ";
|
|
OS << i;
|
|
printComma = true;
|
|
}
|
|
OS << " */";
|
|
|
|
OS << ", " << OMI.CI->Name
|
|
<< ", ";
|
|
|
|
// Write the required features mask.
|
|
if (!II.RequiredFeatures.empty()) {
|
|
for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
|
|
if (i) OS << "|";
|
|
OS << II.RequiredFeatures[i]->getEnumName();
|
|
}
|
|
} else
|
|
OS << "0";
|
|
OS << " },\n";
|
|
}
|
|
OS << "};\n\n";
|
|
|
|
// Emit the operand class switch to call the correct custom parser for
|
|
// the found operand class.
|
|
OS << Target.getName() << ClassName << "::OperandMatchResultTy "
|
|
<< Target.getName() << ClassName << "::\n"
|
|
<< "TryCustomParseOperand(SmallVectorImpl<MCParsedAsmOperand*>"
|
|
<< " &Operands,\n unsigned MCK) {\n\n"
|
|
<< " switch(MCK) {\n";
|
|
|
|
for (std::vector<ClassInfo*>::const_iterator it = Info.Classes.begin(),
|
|
ie = Info.Classes.end(); it != ie; ++it) {
|
|
ClassInfo *CI = *it;
|
|
if (CI->ParserMethod.empty())
|
|
continue;
|
|
OS << " case " << CI->Name << ":\n"
|
|
<< " return " << CI->ParserMethod << "(Operands);\n";
|
|
}
|
|
|
|
OS << " default:\n";
|
|
OS << " return MatchOperand_NoMatch;\n";
|
|
OS << " }\n";
|
|
OS << " return MatchOperand_NoMatch;\n";
|
|
OS << "}\n\n";
|
|
|
|
// Emit the static custom operand parser. This code is very similar with
|
|
// the other matcher. Also use MatchResultTy here just in case we go for
|
|
// a better error handling.
|
|
OS << Target.getName() << ClassName << "::OperandMatchResultTy "
|
|
<< Target.getName() << ClassName << "::\n"
|
|
<< "MatchOperandParserImpl(SmallVectorImpl<MCParsedAsmOperand*>"
|
|
<< " &Operands,\n StringRef Mnemonic) {\n";
|
|
|
|
// Emit code to get the available features.
|
|
OS << " // Get the current feature set.\n";
|
|
OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
|
|
|
|
OS << " // Get the next operand index.\n";
|
|
OS << " unsigned NextOpNum = Operands.size()-1;\n";
|
|
|
|
// Emit code to search the table.
|
|
OS << " // Search the table.\n";
|
|
OS << " std::pair<const OperandMatchEntry*, const OperandMatchEntry*>";
|
|
OS << " MnemonicRange =\n";
|
|
OS << " std::equal_range(OperandMatchTable, OperandMatchTable+"
|
|
<< Info.OperandMatchInfo.size() << ", Mnemonic,\n"
|
|
<< " LessOpcodeOperand());\n\n";
|
|
|
|
OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
|
|
OS << " return MatchOperand_NoMatch;\n\n";
|
|
|
|
OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
|
|
<< " *ie = MnemonicRange.second; it != ie; ++it) {\n";
|
|
|
|
OS << " // equal_range guarantees that instruction mnemonic matches.\n";
|
|
OS << " assert(Mnemonic == it->Mnemonic);\n\n";
|
|
|
|
// Emit check that the required features are available.
|
|
OS << " // check if the available features match\n";
|
|
OS << " if ((AvailableFeatures & it->RequiredFeatures) "
|
|
<< "!= it->RequiredFeatures) {\n";
|
|
OS << " continue;\n";
|
|
OS << " }\n\n";
|
|
|
|
// Emit check to ensure the operand number matches.
|
|
OS << " // check if the operand in question has a custom parser.\n";
|
|
OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
|
|
OS << " continue;\n\n";
|
|
|
|
// Emit call to the custom parser method
|
|
OS << " // call custom parse method to handle the operand\n";
|
|
OS << " OperandMatchResultTy Result = ";
|
|
OS << "TryCustomParseOperand(Operands, it->Class);\n";
|
|
OS << " if (Result != MatchOperand_NoMatch)\n";
|
|
OS << " return Result;\n";
|
|
OS << " }\n\n";
|
|
|
|
OS << " // Okay, we had no match.\n";
|
|
OS << " return MatchOperand_NoMatch;\n";
|
|
OS << "}\n\n";
|
|
}
|
|
|
|
void AsmMatcherEmitter::run(raw_ostream &OS) {
|
|
CodeGenTarget Target(Records);
|
|
Record *AsmParser = Target.getAsmParser();
|
|
std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
|
|
|
|
// Compute the information on the instructions to match.
|
|
AsmMatcherInfo Info(AsmParser, Target, Records);
|
|
Info.BuildInfo();
|
|
|
|
// Sort the instruction table using the partial order on classes. We use
|
|
// stable_sort to ensure that ambiguous instructions are still
|
|
// deterministically ordered.
|
|
std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
|
|
less_ptr<MatchableInfo>());
|
|
|
|
DEBUG_WITH_TYPE("instruction_info", {
|
|
for (std::vector<MatchableInfo*>::iterator
|
|
it = Info.Matchables.begin(), ie = Info.Matchables.end();
|
|
it != ie; ++it)
|
|
(*it)->dump();
|
|
});
|
|
|
|
// Check for ambiguous matchables.
|
|
DEBUG_WITH_TYPE("ambiguous_instrs", {
|
|
unsigned NumAmbiguous = 0;
|
|
for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
|
|
for (unsigned j = i + 1; j != e; ++j) {
|
|
MatchableInfo &A = *Info.Matchables[i];
|
|
MatchableInfo &B = *Info.Matchables[j];
|
|
|
|
if (A.CouldMatchAmbiguouslyWith(B)) {
|
|
errs() << "warning: ambiguous matchables:\n";
|
|
A.dump();
|
|
errs() << "\nis incomparable with:\n";
|
|
B.dump();
|
|
errs() << "\n\n";
|
|
++NumAmbiguous;
|
|
}
|
|
}
|
|
}
|
|
if (NumAmbiguous)
|
|
errs() << "warning: " << NumAmbiguous
|
|
<< " ambiguous matchables!\n";
|
|
});
|
|
|
|
// Compute the information on the custom operand parsing.
|
|
Info.BuildOperandMatchInfo();
|
|
|
|
// Write the output.
|
|
|
|
EmitSourceFileHeader("Assembly Matcher Source Fragment", OS);
|
|
|
|
// Information for the class declaration.
|
|
OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
|
|
OS << "#undef GET_ASSEMBLER_HEADER\n";
|
|
OS << " // This should be included into the middle of the declaration of\n";
|
|
OS << " // your subclasses implementation of MCTargetAsmParser.\n";
|
|
OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const;\n";
|
|
OS << " bool ConvertToMCInst(unsigned Kind, MCInst &Inst, "
|
|
<< "unsigned Opcode,\n"
|
|
<< " const SmallVectorImpl<MCParsedAsmOperand*> "
|
|
<< "&Operands);\n";
|
|
OS << " bool MnemonicIsValid(StringRef Mnemonic);\n";
|
|
OS << " unsigned MatchInstructionImpl(\n";
|
|
OS << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
|
|
OS << " MCInst &Inst, unsigned &ErrorInfo);\n";
|
|
|
|
if (Info.OperandMatchInfo.size()) {
|
|
OS << "\n enum OperandMatchResultTy {\n";
|
|
OS << " MatchOperand_Success, // operand matched successfully\n";
|
|
OS << " MatchOperand_NoMatch, // operand did not match\n";
|
|
OS << " MatchOperand_ParseFail // operand matched but had errors\n";
|
|
OS << " };\n";
|
|
OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
|
|
OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
|
|
OS << " StringRef Mnemonic);\n";
|
|
|
|
OS << " OperandMatchResultTy TryCustomParseOperand(\n";
|
|
OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
|
|
OS << " unsigned MCK);\n\n";
|
|
}
|
|
|
|
OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
|
|
|
|
OS << "\n#ifdef GET_REGISTER_MATCHER\n";
|
|
OS << "#undef GET_REGISTER_MATCHER\n\n";
|
|
|
|
// Emit the subtarget feature enumeration.
|
|
EmitSubtargetFeatureFlagEnumeration(Info, OS);
|
|
|
|
// Emit the function to match a register name to number.
|
|
EmitMatchRegisterName(Target, AsmParser, OS);
|
|
|
|
OS << "#endif // GET_REGISTER_MATCHER\n\n";
|
|
|
|
|
|
OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
|
|
OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
|
|
|
|
// Generate the function that remaps for mnemonic aliases.
|
|
bool HasMnemonicAliases = EmitMnemonicAliases(OS, Info);
|
|
|
|
// Generate the unified function to convert operands into an MCInst.
|
|
EmitConvertToMCInst(Target, ClassName, Info.Matchables, OS);
|
|
|
|
// Emit the enumeration for classes which participate in matching.
|
|
EmitMatchClassEnumeration(Target, Info.Classes, OS);
|
|
|
|
// Emit the routine to match token strings to their match class.
|
|
EmitMatchTokenString(Target, Info.Classes, OS);
|
|
|
|
// Emit the subclass predicate routine.
|
|
EmitIsSubclass(Target, Info.Classes, OS);
|
|
|
|
// Emit the routine to validate an operand against a match class.
|
|
EmitValidateOperandClass(Info, OS);
|
|
|
|
// Emit the available features compute function.
|
|
EmitComputeAvailableFeatures(Info, OS);
|
|
|
|
|
|
size_t MaxNumOperands = 0;
|
|
for (std::vector<MatchableInfo*>::const_iterator it =
|
|
Info.Matchables.begin(), ie = Info.Matchables.end();
|
|
it != ie; ++it)
|
|
MaxNumOperands = std::max(MaxNumOperands, (*it)->AsmOperands.size());
|
|
|
|
// Emit the static match table; unused classes get initalized to 0 which is
|
|
// guaranteed to be InvalidMatchClass.
|
|
//
|
|
// FIXME: We can reduce the size of this table very easily. First, we change
|
|
// it so that store the kinds in separate bit-fields for each index, which
|
|
// only needs to be the max width used for classes at that index (we also need
|
|
// to reject based on this during classification). If we then make sure to
|
|
// order the match kinds appropriately (putting mnemonics last), then we
|
|
// should only end up using a few bits for each class, especially the ones
|
|
// following the mnemonic.
|
|
OS << "namespace {\n";
|
|
OS << " struct MatchEntry {\n";
|
|
OS << " unsigned Opcode;\n";
|
|
OS << " const char *Mnemonic;\n";
|
|
OS << " " << getMinimalTypeForRange(Info.Matchables.size())
|
|
<< " ConvertFn;\n";
|
|
OS << " " << getMinimalTypeForRange(Info.Classes.size())
|
|
<< " Classes[" << MaxNumOperands << "];\n";
|
|
OS << " " << getMinimalTypeForRange(1ULL << Info.SubtargetFeatures.size())
|
|
<< " RequiredFeatures;\n";
|
|
OS << " };\n\n";
|
|
|
|
OS << " // Predicate for searching for an opcode.\n";
|
|
OS << " struct LessOpcode {\n";
|
|
OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
|
|
OS << " return StringRef(LHS.Mnemonic) < RHS;\n";
|
|
OS << " }\n";
|
|
OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
|
|
OS << " return LHS < StringRef(RHS.Mnemonic);\n";
|
|
OS << " }\n";
|
|
OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
|
|
OS << " return StringRef(LHS.Mnemonic) < StringRef(RHS.Mnemonic);\n";
|
|
OS << " }\n";
|
|
OS << " };\n";
|
|
|
|
OS << "} // end anonymous namespace.\n\n";
|
|
|
|
OS << "static const MatchEntry MatchTable["
|
|
<< Info.Matchables.size() << "] = {\n";
|
|
|
|
for (std::vector<MatchableInfo*>::const_iterator it =
|
|
Info.Matchables.begin(), ie = Info.Matchables.end();
|
|
it != ie; ++it) {
|
|
MatchableInfo &II = **it;
|
|
|
|
OS << " { " << Target.getName() << "::"
|
|
<< II.getResultInst()->TheDef->getName() << ", \"" << II.Mnemonic << "\""
|
|
<< ", " << II.ConversionFnKind << ", { ";
|
|
for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
|
|
MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
|
|
|
|
if (i) OS << ", ";
|
|
OS << Op.Class->Name;
|
|
}
|
|
OS << " }, ";
|
|
|
|
// Write the required features mask.
|
|
if (!II.RequiredFeatures.empty()) {
|
|
for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
|
|
if (i) OS << "|";
|
|
OS << II.RequiredFeatures[i]->getEnumName();
|
|
}
|
|
} else
|
|
OS << "0";
|
|
|
|
OS << "},\n";
|
|
}
|
|
|
|
OS << "};\n\n";
|
|
|
|
// A method to determine if a mnemonic is in the list.
|
|
OS << "bool " << Target.getName() << ClassName << "::\n"
|
|
<< "MnemonicIsValid(StringRef Mnemonic) {\n";
|
|
OS << " // Search the table.\n";
|
|
OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
|
|
OS << " std::equal_range(MatchTable, MatchTable+"
|
|
<< Info.Matchables.size() << ", Mnemonic, LessOpcode());\n";
|
|
OS << " return MnemonicRange.first != MnemonicRange.second;\n";
|
|
OS << "}\n\n";
|
|
|
|
// Finally, build the match function.
|
|
OS << "unsigned "
|
|
<< Target.getName() << ClassName << "::\n"
|
|
<< "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
|
|
<< " &Operands,\n";
|
|
OS << " MCInst &Inst, unsigned &ErrorInfo) {\n";
|
|
|
|
// Emit code to get the available features.
|
|
OS << " // Get the current feature set.\n";
|
|
OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
|
|
|
|
OS << " // Get the instruction mnemonic, which is the first token.\n";
|
|
OS << " StringRef Mnemonic = ((" << Target.getName()
|
|
<< "Operand*)Operands[0])->getToken();\n\n";
|
|
|
|
if (HasMnemonicAliases) {
|
|
OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
|
|
OS << " ApplyMnemonicAliases(Mnemonic, AvailableFeatures);\n\n";
|
|
}
|
|
|
|
// Emit code to compute the class list for this operand vector.
|
|
OS << " // Eliminate obvious mismatches.\n";
|
|
OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
|
|
OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
|
|
OS << " return Match_InvalidOperand;\n";
|
|
OS << " }\n\n";
|
|
|
|
OS << " // Some state to try to produce better error messages.\n";
|
|
OS << " bool HadMatchOtherThanFeatures = false;\n";
|
|
OS << " bool HadMatchOtherThanPredicate = false;\n";
|
|
OS << " unsigned RetCode = Match_InvalidOperand;\n";
|
|
OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
|
|
OS << " // wrong for all instances of the instruction.\n";
|
|
OS << " ErrorInfo = ~0U;\n";
|
|
|
|
// Emit code to search the table.
|
|
OS << " // Search the table.\n";
|
|
OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
|
|
OS << " std::equal_range(MatchTable, MatchTable+"
|
|
<< Info.Matchables.size() << ", Mnemonic, LessOpcode());\n\n";
|
|
|
|
OS << " // Return a more specific error code if no mnemonics match.\n";
|
|
OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
|
|
OS << " return Match_MnemonicFail;\n\n";
|
|
|
|
OS << " for (const MatchEntry *it = MnemonicRange.first, "
|
|
<< "*ie = MnemonicRange.second;\n";
|
|
OS << " it != ie; ++it) {\n";
|
|
|
|
OS << " // equal_range guarantees that instruction mnemonic matches.\n";
|
|
OS << " assert(Mnemonic == it->Mnemonic);\n";
|
|
|
|
// Emit check that the subclasses match.
|
|
OS << " bool OperandsValid = true;\n";
|
|
OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
|
|
OS << " if (i + 1 >= Operands.size()) {\n";
|
|
OS << " OperandsValid = (it->Classes[i] == " <<"InvalidMatchClass);\n";
|
|
OS << " break;\n";
|
|
OS << " }\n";
|
|
OS << " if (ValidateOperandClass(Operands[i+1], "
|
|
"(MatchClassKind)it->Classes[i]))\n";
|
|
OS << " continue;\n";
|
|
OS << " // If this operand is broken for all of the instances of this\n";
|
|
OS << " // mnemonic, keep track of it so we can report loc info.\n";
|
|
OS << " if (it == MnemonicRange.first || ErrorInfo <= i+1)\n";
|
|
OS << " ErrorInfo = i+1;\n";
|
|
OS << " // Otherwise, just reject this instance of the mnemonic.\n";
|
|
OS << " OperandsValid = false;\n";
|
|
OS << " break;\n";
|
|
OS << " }\n\n";
|
|
|
|
OS << " if (!OperandsValid) continue;\n";
|
|
|
|
// Emit check that the required features are available.
|
|
OS << " if ((AvailableFeatures & it->RequiredFeatures) "
|
|
<< "!= it->RequiredFeatures) {\n";
|
|
OS << " HadMatchOtherThanFeatures = true;\n";
|
|
OS << " continue;\n";
|
|
OS << " }\n";
|
|
OS << "\n";
|
|
OS << " // We have selected a definite instruction, convert the parsed\n"
|
|
<< " // operands into the appropriate MCInst.\n";
|
|
OS << " if (!ConvertToMCInst(it->ConvertFn, Inst,\n"
|
|
<< " it->Opcode, Operands))\n";
|
|
OS << " return Match_ConversionFail;\n";
|
|
OS << "\n";
|
|
|
|
// Verify the instruction with the target-specific match predicate function.
|
|
OS << " // We have a potential match. Check the target predicate to\n"
|
|
<< " // handle any context sensitive constraints.\n"
|
|
<< " unsigned MatchResult;\n"
|
|
<< " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
|
|
<< " Match_Success) {\n"
|
|
<< " Inst.clear();\n"
|
|
<< " RetCode = MatchResult;\n"
|
|
<< " HadMatchOtherThanPredicate = true;\n"
|
|
<< " continue;\n"
|
|
<< " }\n\n";
|
|
|
|
// Call the post-processing function, if used.
|
|
std::string InsnCleanupFn =
|
|
AsmParser->getValueAsString("AsmParserInstCleanup");
|
|
if (!InsnCleanupFn.empty())
|
|
OS << " " << InsnCleanupFn << "(Inst);\n";
|
|
|
|
OS << " return Match_Success;\n";
|
|
OS << " }\n\n";
|
|
|
|
OS << " // Okay, we had no match. Try to return a useful error code.\n";
|
|
OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)";
|
|
OS << " return RetCode;\n";
|
|
OS << " return Match_MissingFeature;\n";
|
|
OS << "}\n\n";
|
|
|
|
if (Info.OperandMatchInfo.size())
|
|
EmitCustomOperandParsing(OS, Target, Info, ClassName);
|
|
|
|
OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
|
|
}
|