llvm-6502/test/CodeGen/X86/vec-sign.ll
Nate Begeman b65c175d32 Add support for matching psign & plendvb to the x86 target
Remove unnecessary pandn patterns, 'vnot' patfrag looks through bitcasts


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122098 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 22:55:37 +00:00

27 lines
850 B
LLVM

; RUN: llc < %s -mcpu=nehalem | FileCheck %s
define <4 x i32> @psignd(<4 x i32> %a, <4 x i32> %b) nounwind ssp {
entry:
; CHECK: psignd
; CHECK-NOT: sub
%b.lobit = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
%sub = sub nsw <4 x i32> zeroinitializer, %a
%0 = xor <4 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1>
%1 = and <4 x i32> %a, %0
%2 = and <4 x i32> %b.lobit, %sub
%cond = or <4 x i32> %1, %2
ret <4 x i32> %cond
}
define <4 x i32> @pblendvb(<4 x i32> %b, <4 x i32> %a, <4 x i32> %c) nounwind ssp {
entry:
; CHECK: pblendvb
%b.lobit = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
%sub = sub nsw <4 x i32> zeroinitializer, %a
%0 = xor <4 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1>
%1 = and <4 x i32> %c, %0
%2 = and <4 x i32> %a, %b.lobit
%cond = or <4 x i32> %1, %2
ret <4 x i32> %cond
}