mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
170 lines
4.8 KiB
LLVM
170 lines
4.8 KiB
LLVM
; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64 | FileCheck %s
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@var32_0 = global i32 0
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@var32_1 = global i32 0
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@var64_0 = global i64 0
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@var64_1 = global i64 0
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define void @rorv_i64() {
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; CHECK-LABEL: rorv_i64:
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%val0_tmp = load i64, i64* @var64_0
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%val1_tmp = load i64, i64* @var64_1
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%val2_tmp = sub i64 64, %val1_tmp
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%val3_tmp = shl i64 %val0_tmp, %val2_tmp
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%val4_tmp = lshr i64 %val0_tmp, %val1_tmp
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%val5_tmp = or i64 %val3_tmp, %val4_tmp
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; CHECK: {{ror|rorv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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store volatile i64 %val5_tmp, i64* @var64_0
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ret void
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}
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define void @asrv_i64() {
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; CHECK-LABEL: asrv_i64:
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%val0_tmp = load i64, i64* @var64_0
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%val1_tmp = load i64, i64* @var64_1
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%val4_tmp = ashr i64 %val0_tmp, %val1_tmp
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; CHECK: {{asr|asrv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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store volatile i64 %val4_tmp, i64* @var64_1
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ret void
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}
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define void @lsrv_i64() {
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; CHECK-LABEL: lsrv_i64:
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%val0_tmp = load i64, i64* @var64_0
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%val1_tmp = load i64, i64* @var64_1
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%val4_tmp = lshr i64 %val0_tmp, %val1_tmp
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; CHECK: {{lsr|lsrv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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store volatile i64 %val4_tmp, i64* @var64_0
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ret void
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}
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define void @lslv_i64() {
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; CHECK-LABEL: lslv_i64:
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%val0_tmp = load i64, i64* @var64_0
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%val1_tmp = load i64, i64* @var64_1
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%val4_tmp = shl i64 %val0_tmp, %val1_tmp
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; CHECK: {{lsl|lslv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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store volatile i64 %val4_tmp, i64* @var64_1
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ret void
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}
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define void @udiv_i64() {
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; CHECK-LABEL: udiv_i64:
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%val0_tmp = load i64, i64* @var64_0
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%val1_tmp = load i64, i64* @var64_1
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%val4_tmp = udiv i64 %val0_tmp, %val1_tmp
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; CHECK: udiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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store volatile i64 %val4_tmp, i64* @var64_0
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ret void
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}
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define void @sdiv_i64() {
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; CHECK-LABEL: sdiv_i64:
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%val0_tmp = load i64, i64* @var64_0
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%val1_tmp = load i64, i64* @var64_1
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%val4_tmp = sdiv i64 %val0_tmp, %val1_tmp
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; CHECK: sdiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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store volatile i64 %val4_tmp, i64* @var64_1
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ret void
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}
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define void @lsrv_i32() {
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; CHECK-LABEL: lsrv_i32:
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%val0_tmp = load i32, i32* @var32_0
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%val1_tmp = load i32, i32* @var32_1
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%val2_tmp = add i32 1, %val1_tmp
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%val4_tmp = lshr i32 %val0_tmp, %val2_tmp
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; CHECK: {{lsr|lsrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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store volatile i32 %val4_tmp, i32* @var32_0
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ret void
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}
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define void @lslv_i32() {
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; CHECK-LABEL: lslv_i32:
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%val0_tmp = load i32, i32* @var32_0
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%val1_tmp = load i32, i32* @var32_1
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%val2_tmp = add i32 1, %val1_tmp
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%val4_tmp = shl i32 %val0_tmp, %val2_tmp
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; CHECK: {{lsl|lslv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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store volatile i32 %val4_tmp, i32* @var32_1
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ret void
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}
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define void @rorv_i32() {
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; CHECK-LABEL: rorv_i32:
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%val0_tmp = load i32, i32* @var32_0
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%val6_tmp = load i32, i32* @var32_1
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%val1_tmp = add i32 1, %val6_tmp
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%val2_tmp = sub i32 32, %val1_tmp
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%val3_tmp = shl i32 %val0_tmp, %val2_tmp
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%val4_tmp = lshr i32 %val0_tmp, %val1_tmp
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%val5_tmp = or i32 %val3_tmp, %val4_tmp
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; CHECK: {{ror|rorv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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store volatile i32 %val5_tmp, i32* @var32_0
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ret void
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}
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define void @asrv_i32() {
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; CHECK-LABEL: asrv_i32:
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%val0_tmp = load i32, i32* @var32_0
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%val1_tmp = load i32, i32* @var32_1
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%val2_tmp = add i32 1, %val1_tmp
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%val4_tmp = ashr i32 %val0_tmp, %val2_tmp
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; CHECK: {{asr|asrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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store volatile i32 %val4_tmp, i32* @var32_1
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ret void
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}
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define void @sdiv_i32() {
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; CHECK-LABEL: sdiv_i32:
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%val0_tmp = load i32, i32* @var32_0
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%val1_tmp = load i32, i32* @var32_1
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%val4_tmp = sdiv i32 %val0_tmp, %val1_tmp
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; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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store volatile i32 %val4_tmp, i32* @var32_1
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ret void
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}
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define void @udiv_i32() {
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; CHECK-LABEL: udiv_i32:
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%val0_tmp = load i32, i32* @var32_0
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%val1_tmp = load i32, i32* @var32_1
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%val4_tmp = udiv i32 %val0_tmp, %val1_tmp
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; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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store volatile i32 %val4_tmp, i32* @var32_0
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ret void
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}
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; The point of this test is that we may not actually see (shl GPR32:$Val, (zext GPR32:$Val2))
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; in the DAG (the RHS may be natively 64-bit), but we should still use the lsl instructions.
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define i32 @test_lsl32() {
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; CHECK-LABEL: test_lsl32:
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%val = load i32, i32* @var32_0
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%ret = shl i32 1, %val
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; CHECK: {{lsl|lslv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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ret i32 %ret
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}
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define i32 @test_lsr32() {
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; CHECK-LABEL: test_lsr32:
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%val = load i32, i32* @var32_0
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%ret = lshr i32 1, %val
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; CHECK: {{lsr|lsrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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ret i32 %ret
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}
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define i32 @test_asr32(i32 %in) {
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; CHECK-LABEL: test_asr32:
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%val = load i32, i32* @var32_0
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%ret = ashr i32 %in, %val
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; CHECK: {{asr|asrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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ret i32 %ret
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}
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