mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-21 00:32:23 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
810 lines
26 KiB
LLVM
810 lines
26 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=SSE --check-prefix=SSSE3
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
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;
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; Just one 32-bit run to make sure we do reasonable things there.
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=i686 -mattr=+sse4.1 | FileCheck %s --check-prefix=X32-SSE41
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define <8 x i32> @sext_8i16_to_8i32(<8 x i16> %A) nounwind uwtable readnone ssp {
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; SSE2-LABEL: sext_8i16_to_8i32:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movdqa %xmm0, %xmm1
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; SSE2-NEXT: # kill: XMM0<def> XMM1<kill>
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
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; SSE2-NEXT: pslld $16, %xmm0
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; SSE2-NEXT: psrad $16, %xmm0
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; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
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; SSE2-NEXT: pslld $16, %xmm1
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; SSE2-NEXT: psrad $16, %xmm1
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: sext_8i16_to_8i32:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movdqa %xmm0, %xmm1
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; SSSE3-NEXT: # kill: XMM0<def> XMM1<kill>
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; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
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; SSSE3-NEXT: pslld $16, %xmm0
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; SSSE3-NEXT: psrad $16, %xmm0
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; SSSE3-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
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; SSSE3-NEXT: pslld $16, %xmm1
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; SSSE3-NEXT: psrad $16, %xmm1
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: sext_8i16_to_8i32:
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; SSE41: # BB#0: # %entry
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; SSE41-NEXT: movdqa %xmm0, %xmm1
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; SSE41-NEXT: pmovzxwd %xmm1, %xmm0
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; SSE41-NEXT: pslld $16, %xmm0
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; SSE41-NEXT: psrad $16, %xmm0
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; SSE41-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
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; SSE41-NEXT: pslld $16, %xmm1
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; SSE41-NEXT: psrad $16, %xmm1
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: sext_8i16_to_8i32:
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; AVX1: # BB#0: # %entry
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; AVX1-NEXT: vpmovsxwd %xmm0, %xmm1
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; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
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; AVX1-NEXT: vpmovsxwd %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: sext_8i16_to_8i32:
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; AVX2: # BB#0: # %entry
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; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0
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; AVX2-NEXT: retq
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;
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; X32-SSE41-LABEL: sext_8i16_to_8i32:
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; X32-SSE41: # BB#0: # %entry
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; X32-SSE41-NEXT: movdqa %xmm0, %xmm1
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; X32-SSE41-NEXT: pmovzxwd %xmm1, %xmm0
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; X32-SSE41-NEXT: pslld $16, %xmm0
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; X32-SSE41-NEXT: psrad $16, %xmm0
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; X32-SSE41-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
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; X32-SSE41-NEXT: pslld $16, %xmm1
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; X32-SSE41-NEXT: psrad $16, %xmm1
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; X32-SSE41-NEXT: retl
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entry:
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%B = sext <8 x i16> %A to <8 x i32>
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ret <8 x i32>%B
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}
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define <4 x i64> @sext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp {
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; SSE2-LABEL: sext_4i32_to_4i64:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
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; SSE2-NEXT: movd %xmm1, %rax
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; SSE2-NEXT: cltq
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; SSE2-NEXT: movd %rax, %xmm2
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
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; SSE2-NEXT: movd %xmm1, %rax
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; SSE2-NEXT: cltq
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; SSE2-NEXT: movd %rax, %xmm1
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; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
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; SSE2-NEXT: movd %xmm0, %rax
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; SSE2-NEXT: cltq
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; SSE2-NEXT: movd %rax, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
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; SSE2-NEXT: movd %xmm0, %rax
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; SSE2-NEXT: cltq
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; SSE2-NEXT: movd %rax, %xmm0
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; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
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; SSE2-NEXT: movdqa %xmm2, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: sext_4i32_to_4i64:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
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; SSSE3-NEXT: movd %xmm1, %rax
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; SSSE3-NEXT: cltq
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; SSSE3-NEXT: movd %rax, %xmm2
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; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
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; SSSE3-NEXT: movd %xmm1, %rax
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; SSSE3-NEXT: cltq
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; SSSE3-NEXT: movd %rax, %xmm1
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; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
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; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
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; SSSE3-NEXT: movd %xmm0, %rax
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; SSSE3-NEXT: cltq
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; SSSE3-NEXT: movd %rax, %xmm1
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; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
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; SSSE3-NEXT: movd %xmm0, %rax
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; SSSE3-NEXT: cltq
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; SSSE3-NEXT: movd %rax, %xmm0
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; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
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; SSSE3-NEXT: movdqa %xmm2, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: sext_4i32_to_4i64:
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; SSE41: # BB#0: # %entry
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; SSE41-NEXT: pmovzxdq %xmm0, %xmm1
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; SSE41-NEXT: pextrq $1, %xmm1, %rax
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; SSE41-NEXT: cltq
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; SSE41-NEXT: movd %rax, %xmm3
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; SSE41-NEXT: movd %xmm1, %rax
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; SSE41-NEXT: cltq
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; SSE41-NEXT: movd %rax, %xmm2
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; SSE41-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
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; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
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; SSE41-NEXT: pextrq $1, %xmm0, %rax
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; SSE41-NEXT: cltq
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; SSE41-NEXT: movd %rax, %xmm3
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; SSE41-NEXT: movd %xmm0, %rax
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; SSE41-NEXT: cltq
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; SSE41-NEXT: movd %rax, %xmm1
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; SSE41-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
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; SSE41-NEXT: movdqa %xmm2, %xmm0
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: sext_4i32_to_4i64:
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; AVX1: # BB#0: # %entry
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; AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
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; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
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; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: sext_4i32_to_4i64:
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; AVX2: # BB#0: # %entry
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; AVX2-NEXT: vpmovsxdq %xmm0, %ymm0
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; AVX2-NEXT: retq
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;
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; X32-SSE41-LABEL: sext_4i32_to_4i64:
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; X32-SSE41: # BB#0: # %entry
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; X32-SSE41-NEXT: pmovzxdq %xmm0, %xmm2
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; X32-SSE41-NEXT: movd %xmm2, %eax
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; X32-SSE41-NEXT: sarl $31, %eax
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; X32-SSE41-NEXT: pextrd $2, %xmm2, %ecx
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; X32-SSE41-NEXT: pinsrd $1, %eax, %xmm2
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; X32-SSE41-NEXT: sarl $31, %ecx
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; X32-SSE41-NEXT: pinsrd $3, %ecx, %xmm2
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; X32-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,2,3,3]
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; X32-SSE41-NEXT: movd %xmm1, %eax
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; X32-SSE41-NEXT: sarl $31, %eax
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; X32-SSE41-NEXT: pextrd $2, %xmm1, %ecx
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; X32-SSE41-NEXT: pinsrd $1, %eax, %xmm1
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; X32-SSE41-NEXT: sarl $31, %ecx
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; X32-SSE41-NEXT: pinsrd $3, %ecx, %xmm1
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; X32-SSE41-NEXT: movdqa %xmm2, %xmm0
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; X32-SSE41-NEXT: retl
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entry:
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%B = sext <4 x i32> %A to <4 x i64>
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ret <4 x i64>%B
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}
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define <4 x i32> @load_sext_test1(<4 x i16> *%ptr) {
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; SSE2-LABEL: load_sext_test1:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movq (%rdi), %xmm0
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
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; SSE2-NEXT: psrad $16, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: load_sext_test1:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movq (%rdi), %xmm0
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; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
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; SSSE3-NEXT: psrad $16, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: load_sext_test1:
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; SSE41: # BB#0: # %entry
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; SSE41-NEXT: pmovsxwd (%rdi), %xmm0
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: load_sext_test1:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vpmovsxwd (%rdi), %xmm0
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; AVX-NEXT: retq
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;
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; X32-SSE41-LABEL: load_sext_test1:
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; X32-SSE41: # BB#0: # %entry
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; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE41-NEXT: pmovsxwd (%eax), %xmm0
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; X32-SSE41-NEXT: retl
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entry:
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%X = load <4 x i16>, <4 x i16>* %ptr
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%Y = sext <4 x i16> %X to <4 x i32>
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ret <4 x i32>%Y
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}
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define <4 x i32> @load_sext_test2(<4 x i8> *%ptr) {
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; SSE2-LABEL: load_sext_test2:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movd (%rdi), %xmm0
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; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
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; SSE2-NEXT: psrad $24, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: load_sext_test2:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movd (%rdi), %xmm0
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; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
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; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
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; SSSE3-NEXT: psrad $24, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: load_sext_test2:
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; SSE41: # BB#0: # %entry
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; SSE41-NEXT: pmovsxbd (%rdi), %xmm0
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: load_sext_test2:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vpmovsxbd (%rdi), %xmm0
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; AVX-NEXT: retq
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;
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; X32-SSE41-LABEL: load_sext_test2:
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; X32-SSE41: # BB#0: # %entry
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; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE41-NEXT: pmovsxbd (%eax), %xmm0
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; X32-SSE41-NEXT: retl
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entry:
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%X = load <4 x i8>, <4 x i8>* %ptr
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%Y = sext <4 x i8> %X to <4 x i32>
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ret <4 x i32>%Y
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}
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define <2 x i64> @load_sext_test3(<2 x i8> *%ptr) {
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; SSE2-LABEL: load_sext_test3:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movsbq 1(%rdi), %rax
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; SSE2-NEXT: movd %rax, %xmm1
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; SSE2-NEXT: movsbq (%rdi), %rax
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; SSE2-NEXT: movd %rax, %xmm0
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; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: load_sext_test3:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movsbq 1(%rdi), %rax
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; SSSE3-NEXT: movd %rax, %xmm1
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; SSSE3-NEXT: movsbq (%rdi), %rax
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; SSSE3-NEXT: movd %rax, %xmm0
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; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: load_sext_test3:
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; SSE41: # BB#0: # %entry
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; SSE41-NEXT: pmovsxbq (%rdi), %xmm0
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: load_sext_test3:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vpmovsxbq (%rdi), %xmm0
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; AVX-NEXT: retq
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;
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; X32-SSE41-LABEL: load_sext_test3:
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; X32-SSE41: # BB#0: # %entry
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; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE41-NEXT: pmovsxbq (%eax), %xmm0
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; X32-SSE41-NEXT: retl
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entry:
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%X = load <2 x i8>, <2 x i8>* %ptr
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%Y = sext <2 x i8> %X to <2 x i64>
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ret <2 x i64>%Y
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}
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define <2 x i64> @load_sext_test4(<2 x i16> *%ptr) {
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; SSE2-LABEL: load_sext_test4:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movswq 2(%rdi), %rax
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; SSE2-NEXT: movd %rax, %xmm1
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; SSE2-NEXT: movswq (%rdi), %rax
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; SSE2-NEXT: movd %rax, %xmm0
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; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: load_sext_test4:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movswq 2(%rdi), %rax
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; SSSE3-NEXT: movd %rax, %xmm1
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; SSSE3-NEXT: movswq (%rdi), %rax
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; SSSE3-NEXT: movd %rax, %xmm0
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; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: load_sext_test4:
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; SSE41: # BB#0: # %entry
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; SSE41-NEXT: pmovsxwq (%rdi), %xmm0
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; SSE41-NEXT: retq
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;
|
|
; AVX-LABEL: load_sext_test4:
|
|
; AVX: # BB#0: # %entry
|
|
; AVX-NEXT: vpmovsxwq (%rdi), %xmm0
|
|
; AVX-NEXT: retq
|
|
;
|
|
; X32-SSE41-LABEL: load_sext_test4:
|
|
; X32-SSE41: # BB#0: # %entry
|
|
; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
; X32-SSE41-NEXT: pmovsxwq (%eax), %xmm0
|
|
; X32-SSE41-NEXT: retl
|
|
entry:
|
|
%X = load <2 x i16>, <2 x i16>* %ptr
|
|
%Y = sext <2 x i16> %X to <2 x i64>
|
|
ret <2 x i64>%Y
|
|
}
|
|
|
|
define <2 x i64> @load_sext_test5(<2 x i32> *%ptr) {
|
|
; SSE2-LABEL: load_sext_test5:
|
|
; SSE2: # BB#0: # %entry
|
|
; SSE2-NEXT: movslq 4(%rdi), %rax
|
|
; SSE2-NEXT: movd %rax, %xmm1
|
|
; SSE2-NEXT: movslq (%rdi), %rax
|
|
; SSE2-NEXT: movd %rax, %xmm0
|
|
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
|
; SSE2-NEXT: retq
|
|
;
|
|
; SSSE3-LABEL: load_sext_test5:
|
|
; SSSE3: # BB#0: # %entry
|
|
; SSSE3-NEXT: movslq 4(%rdi), %rax
|
|
; SSSE3-NEXT: movd %rax, %xmm1
|
|
; SSSE3-NEXT: movslq (%rdi), %rax
|
|
; SSSE3-NEXT: movd %rax, %xmm0
|
|
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
|
; SSSE3-NEXT: retq
|
|
;
|
|
; SSE41-LABEL: load_sext_test5:
|
|
; SSE41: # BB#0: # %entry
|
|
; SSE41-NEXT: pmovsxdq (%rdi), %xmm0
|
|
; SSE41-NEXT: retq
|
|
;
|
|
; AVX-LABEL: load_sext_test5:
|
|
; AVX: # BB#0: # %entry
|
|
; AVX-NEXT: vpmovsxdq (%rdi), %xmm0
|
|
; AVX-NEXT: retq
|
|
;
|
|
; X32-SSE41-LABEL: load_sext_test5:
|
|
; X32-SSE41: # BB#0: # %entry
|
|
; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
; X32-SSE41-NEXT: pmovsxdq (%eax), %xmm0
|
|
; X32-SSE41-NEXT: retl
|
|
entry:
|
|
%X = load <2 x i32>, <2 x i32>* %ptr
|
|
%Y = sext <2 x i32> %X to <2 x i64>
|
|
ret <2 x i64>%Y
|
|
}
|
|
|
|
define <8 x i16> @load_sext_test6(<8 x i8> *%ptr) {
|
|
; SSE2-LABEL: load_sext_test6:
|
|
; SSE2: # BB#0: # %entry
|
|
; SSE2-NEXT: movq (%rdi), %xmm0
|
|
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
|
|
; SSE2-NEXT: psraw $8, %xmm0
|
|
; SSE2-NEXT: retq
|
|
;
|
|
; SSSE3-LABEL: load_sext_test6:
|
|
; SSSE3: # BB#0: # %entry
|
|
; SSSE3-NEXT: movq (%rdi), %xmm0
|
|
; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
|
|
; SSSE3-NEXT: psraw $8, %xmm0
|
|
; SSSE3-NEXT: retq
|
|
;
|
|
; SSE41-LABEL: load_sext_test6:
|
|
; SSE41: # BB#0: # %entry
|
|
; SSE41-NEXT: pmovsxbw (%rdi), %xmm0
|
|
; SSE41-NEXT: retq
|
|
;
|
|
; AVX-LABEL: load_sext_test6:
|
|
; AVX: # BB#0: # %entry
|
|
; AVX-NEXT: vpmovsxbw (%rdi), %xmm0
|
|
; AVX-NEXT: retq
|
|
;
|
|
; X32-SSE41-LABEL: load_sext_test6:
|
|
; X32-SSE41: # BB#0: # %entry
|
|
; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
; X32-SSE41-NEXT: pmovsxbw (%eax), %xmm0
|
|
; X32-SSE41-NEXT: retl
|
|
entry:
|
|
%X = load <8 x i8>, <8 x i8>* %ptr
|
|
%Y = sext <8 x i8> %X to <8 x i16>
|
|
ret <8 x i16>%Y
|
|
}
|
|
|
|
define <4 x i64> @sext_4i1_to_4i64(<4 x i1> %mask) {
|
|
; SSE2-LABEL: sext_4i1_to_4i64:
|
|
; SSE2: # BB#0:
|
|
; SSE2-NEXT: pslld $31, %xmm0
|
|
; SSE2-NEXT: psrad $31, %xmm0
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
|
|
; SSE2-NEXT: movd %xmm1, %rax
|
|
; SSE2-NEXT: cltq
|
|
; SSE2-NEXT: movd %rax, %xmm2
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
|
|
; SSE2-NEXT: movd %xmm1, %rax
|
|
; SSE2-NEXT: cltq
|
|
; SSE2-NEXT: movd %rax, %xmm1
|
|
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
|
|
; SSE2-NEXT: movd %xmm0, %rax
|
|
; SSE2-NEXT: cltq
|
|
; SSE2-NEXT: movd %rax, %xmm1
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
|
; SSE2-NEXT: movd %xmm0, %rax
|
|
; SSE2-NEXT: cltq
|
|
; SSE2-NEXT: movd %rax, %xmm0
|
|
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
|
|
; SSE2-NEXT: movdqa %xmm2, %xmm0
|
|
; SSE2-NEXT: retq
|
|
;
|
|
; SSSE3-LABEL: sext_4i1_to_4i64:
|
|
; SSSE3: # BB#0:
|
|
; SSSE3-NEXT: pslld $31, %xmm0
|
|
; SSSE3-NEXT: psrad $31, %xmm0
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
|
|
; SSSE3-NEXT: movd %xmm1, %rax
|
|
; SSSE3-NEXT: cltq
|
|
; SSSE3-NEXT: movd %rax, %xmm2
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
|
|
; SSSE3-NEXT: movd %xmm1, %rax
|
|
; SSSE3-NEXT: cltq
|
|
; SSSE3-NEXT: movd %rax, %xmm1
|
|
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
|
|
; SSSE3-NEXT: movd %xmm0, %rax
|
|
; SSSE3-NEXT: cltq
|
|
; SSSE3-NEXT: movd %rax, %xmm1
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
|
; SSSE3-NEXT: movd %xmm0, %rax
|
|
; SSSE3-NEXT: cltq
|
|
; SSSE3-NEXT: movd %rax, %xmm0
|
|
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
|
|
; SSSE3-NEXT: movdqa %xmm2, %xmm0
|
|
; SSSE3-NEXT: retq
|
|
;
|
|
; SSE41-LABEL: sext_4i1_to_4i64:
|
|
; SSE41: # BB#0:
|
|
; SSE41-NEXT: pslld $31, %xmm0
|
|
; SSE41-NEXT: psrad $31, %xmm0
|
|
; SSE41-NEXT: pmovzxdq %xmm0, %xmm1
|
|
; SSE41-NEXT: pextrq $1, %xmm1, %rax
|
|
; SSE41-NEXT: cltq
|
|
; SSE41-NEXT: movd %rax, %xmm3
|
|
; SSE41-NEXT: movd %xmm1, %rax
|
|
; SSE41-NEXT: cltq
|
|
; SSE41-NEXT: movd %rax, %xmm2
|
|
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
|
|
; SSE41-NEXT: pextrq $1, %xmm0, %rax
|
|
; SSE41-NEXT: cltq
|
|
; SSE41-NEXT: movd %rax, %xmm3
|
|
; SSE41-NEXT: movd %xmm0, %rax
|
|
; SSE41-NEXT: cltq
|
|
; SSE41-NEXT: movd %rax, %xmm1
|
|
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
|
|
; SSE41-NEXT: movdqa %xmm2, %xmm0
|
|
; SSE41-NEXT: retq
|
|
;
|
|
; AVX1-LABEL: sext_4i1_to_4i64:
|
|
; AVX1: # BB#0:
|
|
; AVX1-NEXT: vpslld $31, %xmm0, %xmm0
|
|
; AVX1-NEXT: vpsrad $31, %xmm0, %xmm0
|
|
; AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
|
|
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
|
; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
|
|
; AVX1-NEXT: retq
|
|
;
|
|
; AVX2-LABEL: sext_4i1_to_4i64:
|
|
; AVX2: # BB#0:
|
|
; AVX2-NEXT: vpslld $31, %xmm0, %xmm0
|
|
; AVX2-NEXT: vpsrad $31, %xmm0, %xmm0
|
|
; AVX2-NEXT: vpmovsxdq %xmm0, %ymm0
|
|
; AVX2-NEXT: retq
|
|
;
|
|
; X32-SSE41-LABEL: sext_4i1_to_4i64:
|
|
; X32-SSE41: # BB#0:
|
|
; X32-SSE41-NEXT: pslld $31, %xmm0
|
|
; X32-SSE41-NEXT: psrad $31, %xmm0
|
|
; X32-SSE41-NEXT: pmovzxdq %xmm0, %xmm2
|
|
; X32-SSE41-NEXT: movd %xmm2, %eax
|
|
; X32-SSE41-NEXT: sarl $31, %eax
|
|
; X32-SSE41-NEXT: pextrd $2, %xmm2, %ecx
|
|
; X32-SSE41-NEXT: pinsrd $1, %eax, %xmm2
|
|
; X32-SSE41-NEXT: sarl $31, %ecx
|
|
; X32-SSE41-NEXT: pinsrd $3, %ecx, %xmm2
|
|
; X32-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,2,3,3]
|
|
; X32-SSE41-NEXT: movd %xmm1, %eax
|
|
; X32-SSE41-NEXT: sarl $31, %eax
|
|
; X32-SSE41-NEXT: pextrd $2, %xmm1, %ecx
|
|
; X32-SSE41-NEXT: pinsrd $1, %eax, %xmm1
|
|
; X32-SSE41-NEXT: sarl $31, %ecx
|
|
; X32-SSE41-NEXT: pinsrd $3, %ecx, %xmm1
|
|
; X32-SSE41-NEXT: movdqa %xmm2, %xmm0
|
|
; X32-SSE41-NEXT: retl
|
|
%extmask = sext <4 x i1> %mask to <4 x i64>
|
|
ret <4 x i64> %extmask
|
|
}
|
|
|
|
define <16 x i16> @sext_16i8_to_16i16(<16 x i8> *%ptr) {
|
|
; SSE2-LABEL: sext_16i8_to_16i16:
|
|
; SSE2: # BB#0: # %entry
|
|
; SSE2-NEXT: movq (%rdi), %xmm0
|
|
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
|
|
; SSE2-NEXT: psraw $8, %xmm0
|
|
; SSE2-NEXT: movq 8(%rdi), %xmm1
|
|
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
|
|
; SSE2-NEXT: psraw $8, %xmm1
|
|
; SSE2-NEXT: retq
|
|
;
|
|
; SSSE3-LABEL: sext_16i8_to_16i16:
|
|
; SSSE3: # BB#0: # %entry
|
|
; SSSE3-NEXT: movq (%rdi), %xmm0
|
|
; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
|
|
; SSSE3-NEXT: psraw $8, %xmm0
|
|
; SSSE3-NEXT: movq 8(%rdi), %xmm1
|
|
; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
|
|
; SSSE3-NEXT: psraw $8, %xmm1
|
|
; SSSE3-NEXT: retq
|
|
;
|
|
; SSE41-LABEL: sext_16i8_to_16i16:
|
|
; SSE41: # BB#0: # %entry
|
|
; SSE41-NEXT: pmovsxbw (%rdi), %xmm0
|
|
; SSE41-NEXT: pmovsxbw 8(%rdi), %xmm1
|
|
; SSE41-NEXT: retq
|
|
;
|
|
; AVX1-LABEL: sext_16i8_to_16i16:
|
|
; AVX1: # BB#0: # %entry
|
|
; AVX1-NEXT: vpmovsxbw (%rdi), %xmm0
|
|
; AVX1-NEXT: vpmovsxbw 8(%rdi), %xmm1
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
|
; AVX1-NEXT: retq
|
|
;
|
|
; AVX2-LABEL: sext_16i8_to_16i16:
|
|
; AVX2: # BB#0: # %entry
|
|
; AVX2-NEXT: vpmovsxbw (%rdi), %ymm0
|
|
; AVX2-NEXT: retq
|
|
;
|
|
; X32-SSE41-LABEL: sext_16i8_to_16i16:
|
|
; X32-SSE41: # BB#0: # %entry
|
|
; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
; X32-SSE41-NEXT: pmovsxbw (%eax), %xmm0
|
|
; X32-SSE41-NEXT: pmovsxbw 8(%eax), %xmm1
|
|
; X32-SSE41-NEXT: retl
|
|
entry:
|
|
%X = load <16 x i8>, <16 x i8>* %ptr
|
|
%Y = sext <16 x i8> %X to <16 x i16>
|
|
ret <16 x i16> %Y
|
|
}
|
|
|
|
define <4 x i64> @sext_4i8_to_4i64(<4 x i8> %mask) {
|
|
; SSE2-LABEL: sext_4i8_to_4i64:
|
|
; SSE2: # BB#0:
|
|
; SSE2-NEXT: pslld $24, %xmm0
|
|
; SSE2-NEXT: psrad $24, %xmm0
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
|
|
; SSE2-NEXT: movd %xmm1, %rax
|
|
; SSE2-NEXT: cltq
|
|
; SSE2-NEXT: movd %rax, %xmm2
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
|
|
; SSE2-NEXT: movd %xmm1, %rax
|
|
; SSE2-NEXT: cltq
|
|
; SSE2-NEXT: movd %rax, %xmm1
|
|
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
|
|
; SSE2-NEXT: movd %xmm0, %rax
|
|
; SSE2-NEXT: cltq
|
|
; SSE2-NEXT: movd %rax, %xmm1
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
|
; SSE2-NEXT: movd %xmm0, %rax
|
|
; SSE2-NEXT: cltq
|
|
; SSE2-NEXT: movd %rax, %xmm0
|
|
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
|
|
; SSE2-NEXT: movdqa %xmm2, %xmm0
|
|
; SSE2-NEXT: retq
|
|
;
|
|
; SSSE3-LABEL: sext_4i8_to_4i64:
|
|
; SSSE3: # BB#0:
|
|
; SSSE3-NEXT: pslld $24, %xmm0
|
|
; SSSE3-NEXT: psrad $24, %xmm0
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
|
|
; SSSE3-NEXT: movd %xmm1, %rax
|
|
; SSSE3-NEXT: cltq
|
|
; SSSE3-NEXT: movd %rax, %xmm2
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
|
|
; SSSE3-NEXT: movd %xmm1, %rax
|
|
; SSSE3-NEXT: cltq
|
|
; SSSE3-NEXT: movd %rax, %xmm1
|
|
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
|
|
; SSSE3-NEXT: movd %xmm0, %rax
|
|
; SSSE3-NEXT: cltq
|
|
; SSSE3-NEXT: movd %rax, %xmm1
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
|
; SSSE3-NEXT: movd %xmm0, %rax
|
|
; SSSE3-NEXT: cltq
|
|
; SSSE3-NEXT: movd %rax, %xmm0
|
|
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
|
|
; SSSE3-NEXT: movdqa %xmm2, %xmm0
|
|
; SSSE3-NEXT: retq
|
|
;
|
|
; SSE41-LABEL: sext_4i8_to_4i64:
|
|
; SSE41: # BB#0:
|
|
; SSE41-NEXT: pslld $24, %xmm0
|
|
; SSE41-NEXT: psrad $24, %xmm0
|
|
; SSE41-NEXT: pmovzxdq %xmm0, %xmm1
|
|
; SSE41-NEXT: pextrq $1, %xmm1, %rax
|
|
; SSE41-NEXT: cltq
|
|
; SSE41-NEXT: movd %rax, %xmm3
|
|
; SSE41-NEXT: movd %xmm1, %rax
|
|
; SSE41-NEXT: cltq
|
|
; SSE41-NEXT: movd %rax, %xmm2
|
|
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
|
|
; SSE41-NEXT: pextrq $1, %xmm0, %rax
|
|
; SSE41-NEXT: cltq
|
|
; SSE41-NEXT: movd %rax, %xmm3
|
|
; SSE41-NEXT: movd %xmm0, %rax
|
|
; SSE41-NEXT: cltq
|
|
; SSE41-NEXT: movd %rax, %xmm1
|
|
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
|
|
; SSE41-NEXT: movdqa %xmm2, %xmm0
|
|
; SSE41-NEXT: retq
|
|
;
|
|
; AVX1-LABEL: sext_4i8_to_4i64:
|
|
; AVX1: # BB#0:
|
|
; AVX1-NEXT: vpslld $24, %xmm0, %xmm0
|
|
; AVX1-NEXT: vpsrad $24, %xmm0, %xmm0
|
|
; AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
|
|
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
|
; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
|
|
; AVX1-NEXT: retq
|
|
;
|
|
; AVX2-LABEL: sext_4i8_to_4i64:
|
|
; AVX2: # BB#0:
|
|
; AVX2-NEXT: vpslld $24, %xmm0, %xmm0
|
|
; AVX2-NEXT: vpsrad $24, %xmm0, %xmm0
|
|
; AVX2-NEXT: vpmovsxdq %xmm0, %ymm0
|
|
; AVX2-NEXT: retq
|
|
;
|
|
; X32-SSE41-LABEL: sext_4i8_to_4i64:
|
|
; X32-SSE41: # BB#0:
|
|
; X32-SSE41-NEXT: pslld $24, %xmm0
|
|
; X32-SSE41-NEXT: psrad $24, %xmm0
|
|
; X32-SSE41-NEXT: pmovzxdq %xmm0, %xmm2
|
|
; X32-SSE41-NEXT: movd %xmm2, %eax
|
|
; X32-SSE41-NEXT: sarl $31, %eax
|
|
; X32-SSE41-NEXT: pextrd $2, %xmm2, %ecx
|
|
; X32-SSE41-NEXT: pinsrd $1, %eax, %xmm2
|
|
; X32-SSE41-NEXT: sarl $31, %ecx
|
|
; X32-SSE41-NEXT: pinsrd $3, %ecx, %xmm2
|
|
; X32-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,2,3,3]
|
|
; X32-SSE41-NEXT: movd %xmm1, %eax
|
|
; X32-SSE41-NEXT: sarl $31, %eax
|
|
; X32-SSE41-NEXT: pextrd $2, %xmm1, %ecx
|
|
; X32-SSE41-NEXT: pinsrd $1, %eax, %xmm1
|
|
; X32-SSE41-NEXT: sarl $31, %ecx
|
|
; X32-SSE41-NEXT: pinsrd $3, %ecx, %xmm1
|
|
; X32-SSE41-NEXT: movdqa %xmm2, %xmm0
|
|
; X32-SSE41-NEXT: retl
|
|
%extmask = sext <4 x i8> %mask to <4 x i64>
|
|
ret <4 x i64> %extmask
|
|
}
|
|
|
|
define <4 x i64> @load_sext_4i8_to_4i64(<4 x i8> *%ptr) {
|
|
; SSE2-LABEL: load_sext_4i8_to_4i64:
|
|
; SSE2: # BB#0: # %entry
|
|
; SSE2-NEXT: movsbq 1(%rdi), %rax
|
|
; SSE2-NEXT: movd %rax, %xmm1
|
|
; SSE2-NEXT: movsbq (%rdi), %rax
|
|
; SSE2-NEXT: movd %rax, %xmm0
|
|
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
|
; SSE2-NEXT: movsbq 3(%rdi), %rax
|
|
; SSE2-NEXT: movd %rax, %xmm2
|
|
; SSE2-NEXT: movsbq 2(%rdi), %rax
|
|
; SSE2-NEXT: movd %rax, %xmm1
|
|
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
|
|
; SSE2-NEXT: retq
|
|
;
|
|
; SSSE3-LABEL: load_sext_4i8_to_4i64:
|
|
; SSSE3: # BB#0: # %entry
|
|
; SSSE3-NEXT: movsbq 1(%rdi), %rax
|
|
; SSSE3-NEXT: movd %rax, %xmm1
|
|
; SSSE3-NEXT: movsbq (%rdi), %rax
|
|
; SSSE3-NEXT: movd %rax, %xmm0
|
|
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
|
; SSSE3-NEXT: movsbq 3(%rdi), %rax
|
|
; SSSE3-NEXT: movd %rax, %xmm2
|
|
; SSSE3-NEXT: movsbq 2(%rdi), %rax
|
|
; SSSE3-NEXT: movd %rax, %xmm1
|
|
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
|
|
; SSSE3-NEXT: retq
|
|
;
|
|
; SSE41-LABEL: load_sext_4i8_to_4i64:
|
|
; SSE41: # BB#0: # %entry
|
|
; SSE41-NEXT: pmovsxbq (%rdi), %xmm0
|
|
; SSE41-NEXT: pmovsxbq 2(%rdi), %xmm1
|
|
; SSE41-NEXT: retq
|
|
;
|
|
; AVX1-LABEL: load_sext_4i8_to_4i64:
|
|
; AVX1: # BB#0: # %entry
|
|
; AVX1-NEXT: vpmovsxbd (%rdi), %xmm0
|
|
; AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
|
|
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
|
; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
|
|
; AVX1-NEXT: retq
|
|
;
|
|
; AVX2-LABEL: load_sext_4i8_to_4i64:
|
|
; AVX2: # BB#0: # %entry
|
|
; AVX2-NEXT: vpmovsxbq (%rdi), %ymm0
|
|
; AVX2-NEXT: retq
|
|
;
|
|
; X32-SSE41-LABEL: load_sext_4i8_to_4i64:
|
|
; X32-SSE41: # BB#0: # %entry
|
|
; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
; X32-SSE41-NEXT: pmovsxbq (%eax), %xmm0
|
|
; X32-SSE41-NEXT: pmovsxbq 2(%eax), %xmm1
|
|
; X32-SSE41-NEXT: retl
|
|
entry:
|
|
%X = load <4 x i8>, <4 x i8>* %ptr
|
|
%Y = sext <4 x i8> %X to <4 x i64>
|
|
ret <4 x i64>%Y
|
|
}
|
|
|
|
define <4 x i64> @load_sext_4i16_to_4i64(<4 x i16> *%ptr) {
|
|
; SSE2-LABEL: load_sext_4i16_to_4i64:
|
|
; SSE2: # BB#0: # %entry
|
|
; SSE2-NEXT: movswq 2(%rdi), %rax
|
|
; SSE2-NEXT: movd %rax, %xmm1
|
|
; SSE2-NEXT: movswq (%rdi), %rax
|
|
; SSE2-NEXT: movd %rax, %xmm0
|
|
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
|
; SSE2-NEXT: movswq 6(%rdi), %rax
|
|
; SSE2-NEXT: movd %rax, %xmm2
|
|
; SSE2-NEXT: movswq 4(%rdi), %rax
|
|
; SSE2-NEXT: movd %rax, %xmm1
|
|
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
|
|
; SSE2-NEXT: retq
|
|
;
|
|
; SSSE3-LABEL: load_sext_4i16_to_4i64:
|
|
; SSSE3: # BB#0: # %entry
|
|
; SSSE3-NEXT: movswq 2(%rdi), %rax
|
|
; SSSE3-NEXT: movd %rax, %xmm1
|
|
; SSSE3-NEXT: movswq (%rdi), %rax
|
|
; SSSE3-NEXT: movd %rax, %xmm0
|
|
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
|
; SSSE3-NEXT: movswq 6(%rdi), %rax
|
|
; SSSE3-NEXT: movd %rax, %xmm2
|
|
; SSSE3-NEXT: movswq 4(%rdi), %rax
|
|
; SSSE3-NEXT: movd %rax, %xmm1
|
|
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
|
|
; SSSE3-NEXT: retq
|
|
;
|
|
; SSE41-LABEL: load_sext_4i16_to_4i64:
|
|
; SSE41: # BB#0: # %entry
|
|
; SSE41-NEXT: pmovsxwq (%rdi), %xmm0
|
|
; SSE41-NEXT: pmovsxwq 4(%rdi), %xmm1
|
|
; SSE41-NEXT: retq
|
|
;
|
|
; AVX1-LABEL: load_sext_4i16_to_4i64:
|
|
; AVX1: # BB#0: # %entry
|
|
; AVX1-NEXT: vpmovsxwd (%rdi), %xmm0
|
|
; AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
|
|
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
|
; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
|
|
; AVX1-NEXT: retq
|
|
;
|
|
; AVX2-LABEL: load_sext_4i16_to_4i64:
|
|
; AVX2: # BB#0: # %entry
|
|
; AVX2-NEXT: vpmovsxwq (%rdi), %ymm0
|
|
; AVX2-NEXT: retq
|
|
;
|
|
; X32-SSE41-LABEL: load_sext_4i16_to_4i64:
|
|
; X32-SSE41: # BB#0: # %entry
|
|
; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
; X32-SSE41-NEXT: pmovsxwq (%eax), %xmm0
|
|
; X32-SSE41-NEXT: pmovsxwq 4(%eax), %xmm1
|
|
; X32-SSE41-NEXT: retl
|
|
entry:
|
|
%X = load <4 x i16>, <4 x i16>* %ptr
|
|
%Y = sext <4 x i16> %X to <4 x i64>
|
|
ret <4 x i64>%Y
|
|
}
|