Akira Hatanaka b66510f309 In MipsDisassembler.cpp, instead of defining register class tables, use the ones ... that are generated by TableGen and are already available in MipsGenRegisterInfo.inc. Suggested by Jakob Stoklund Olesen. Also, fix bug in function DecodeAFGR64RegisterClass. Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158846 91177308-0d34-0410-b5e6-96231b3b80d8		2012-06-20 20:39:23 +00:00
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ARM	Correct decoder for T1 conditional B encoding	2012-06-06 09:12:53 +00:00
MBlaze	Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu	2012-03-25 09:02:19 +00:00
Mips	In MipsDisassembler.cpp, instead of defining register class tables, use the ones	2012-06-20 20:39:23 +00:00
X86	Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions.	2012-05-29 19:05:25 +00:00