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343f0c0467
is currently off by default, and can be enabled with -disable-post-RA-scheduler=false. This doesn't have a significant impact on most code yet because it doesn't yet do anything to address anti-dependencies and it doesn't attempt to disambiguate memory references. Also, several popular targets don't have pipeline descriptions yet. The majority of the changes here are splitting the SelectionDAG-specific code out of ScheduleDAG, so that ScheduleDAG can be moved to libLLVMCodeGen.a. The interface between ScheduleDAG-using code and the rest of the scheduling code is somewhat rough and will evolve. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59676 91177308-0d34-0410-b5e6-96231b3b80d8
74 lines
2.6 KiB
C++
74 lines
2.6 KiB
C++
//===-- PPCHazardRecognizers.h - PowerPC Hazard Recognizers -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines hazard recognizers for scheduling on PowerPC processors.
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//
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//===----------------------------------------------------------------------===//
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#ifndef PPCHAZRECS_H
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#define PPCHAZRECS_H
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#include "llvm/CodeGen/ScheduleDAGSDNodes.h"
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#include "PPCInstrInfo.h"
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namespace llvm {
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/// PPCHazardRecognizer970 - This class defines a finite state automata that
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/// models the dispatch logic on the PowerPC 970 (aka G5) processor. This
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/// promotes good dispatch group formation and implements noop insertion to
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/// avoid structural hazards that cause significant performance penalties (e.g.
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/// setting the CTR register then branching through it within a dispatch group),
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/// or storing then loading from the same address within a dispatch group.
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class PPCHazardRecognizer970 : public HazardRecognizer {
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const TargetInstrInfo &TII;
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unsigned NumIssued; // Number of insts issued, including advanced cycles.
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// Various things that can cause a structural hazard.
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// HasCTRSet - If the CTR register is set in this group, disallow BCTRL.
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bool HasCTRSet;
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// StoredPtr - Keep track of the address of any store. If we see a load from
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// the same address (or one that aliases it), disallow the store. We can have
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// up to four stores in one dispatch group, hence we track up to 4.
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//
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// This is null if we haven't seen a store yet. We keep track of both
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// operands of the store here, since we support [r+r] and [r+i] addressing.
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SDValue StorePtr1[4], StorePtr2[4];
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unsigned StoreSize[4];
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unsigned NumStores;
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public:
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PPCHazardRecognizer970(const TargetInstrInfo &TII);
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virtual HazardType getHazardType(SDNode *Node);
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virtual void EmitInstruction(SDNode *Node);
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virtual void AdvanceCycle();
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virtual void EmitNoop();
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private:
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/// EndDispatchGroup - Called when we are finishing a new dispatch group.
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///
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void EndDispatchGroup();
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/// GetInstrType - Classify the specified powerpc opcode according to its
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/// pipeline.
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PPCII::PPC970_Unit GetInstrType(unsigned Opcode,
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bool &isFirst, bool &isSingle,bool &isCracked,
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bool &isLoad, bool &isStore);
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bool isLoadOfStoredAddress(unsigned LoadSize,
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SDValue Ptr1, SDValue Ptr2) const;
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};
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} // end namespace llvm
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#endif
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