mirror of
https://github.com/c64scene-ar/llvm-6502.git
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1733124507
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76029 91177308-0d34-0410-b5e6-96231b3b80d8
425 lines
14 KiB
C++
425 lines
14 KiB
C++
//===- SystemZInstrInfo.cpp - SystemZ Instruction Information --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SystemZ implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZ.h"
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#include "SystemZInstrBuilder.h"
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#include "SystemZInstrInfo.h"
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#include "SystemZMachineFunctionInfo.h"
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#include "SystemZTargetMachine.h"
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#include "SystemZGenInstrInfo.inc"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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using namespace llvm;
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SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
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: TargetInstrInfoImpl(SystemZInsts, array_lengthof(SystemZInsts)),
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RI(tm, *this), TM(tm) {
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// Fill the spill offsets map
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static const unsigned SpillOffsTab[][2] = {
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{ SystemZ::R2D, 0x10 },
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{ SystemZ::R3D, 0x18 },
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{ SystemZ::R4D, 0x20 },
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{ SystemZ::R5D, 0x28 },
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{ SystemZ::R6D, 0x30 },
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{ SystemZ::R7D, 0x38 },
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{ SystemZ::R8D, 0x40 },
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{ SystemZ::R9D, 0x48 },
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{ SystemZ::R10D, 0x50 },
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{ SystemZ::R11D, 0x58 },
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{ SystemZ::R12D, 0x60 },
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{ SystemZ::R13D, 0x68 },
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{ SystemZ::R14D, 0x70 },
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{ SystemZ::R15D, 0x78 }
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};
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RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS);
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for (unsigned i = 0, e = array_lengthof(SpillOffsTab); i != e; ++i)
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RegSpillOffsets[SpillOffsTab[i][0]] = SpillOffsTab[i][1];
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}
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void SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIdx,
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const TargetRegisterClass *RC) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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unsigned Opc = 0;
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if (RC == &SystemZ::GR32RegClass ||
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RC == &SystemZ::ADDR32RegClass)
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Opc = SystemZ::MOV32mr;
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else if (RC == &SystemZ::GR64RegClass ||
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RC == &SystemZ::ADDR64RegClass) {
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Opc = SystemZ::MOV64mr;
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} else if (RC == &SystemZ::FP32RegClass) {
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Opc = SystemZ::FMOV32mr;
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} else if (RC == &SystemZ::FP64RegClass) {
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Opc = SystemZ::FMOV64mr;
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} else
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assert(0 && "Unsupported regclass to store");
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addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
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.addReg(SrcReg, getKillRegState(isKill));
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}
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void SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC) const{
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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unsigned Opc = 0;
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if (RC == &SystemZ::GR32RegClass ||
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RC == &SystemZ::ADDR32RegClass)
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Opc = SystemZ::MOV32rm;
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else if (RC == &SystemZ::GR64RegClass ||
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RC == &SystemZ::ADDR64RegClass) {
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Opc = SystemZ::MOV64rm;
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} else if (RC == &SystemZ::FP32RegClass) {
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Opc = SystemZ::FMOV32rm;
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} else if (RC == &SystemZ::FP64RegClass) {
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Opc = SystemZ::FMOV64rm;
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} else
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assert(0 && "Unsupported regclass to store");
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addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
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}
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bool SystemZInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (I != MBB.end()) DL = I->getDebugLoc();
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// Determine if DstRC and SrcRC have a common superclass.
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const TargetRegisterClass *CommonRC = DestRC;
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if (DestRC == SrcRC)
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/* Same regclass for source and dest */;
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else if (CommonRC->hasSuperClass(SrcRC))
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CommonRC = SrcRC;
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else if (!CommonRC->hasSubClass(SrcRC))
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CommonRC = 0;
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if (CommonRC) {
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if (CommonRC == &SystemZ::GR64RegClass ||
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CommonRC == &SystemZ::ADDR64RegClass) {
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BuildMI(MBB, I, DL, get(SystemZ::MOV64rr), DestReg).addReg(SrcReg);
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} else if (CommonRC == &SystemZ::GR32RegClass ||
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CommonRC == &SystemZ::ADDR32RegClass) {
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BuildMI(MBB, I, DL, get(SystemZ::MOV32rr), DestReg).addReg(SrcReg);
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} else if (CommonRC == &SystemZ::GR64PRegClass) {
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BuildMI(MBB, I, DL, get(SystemZ::MOV64rrP), DestReg).addReg(SrcReg);
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} else if (CommonRC == &SystemZ::GR128RegClass) {
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BuildMI(MBB, I, DL, get(SystemZ::MOV128rr), DestReg).addReg(SrcReg);
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} else if (CommonRC == &SystemZ::FP32RegClass) {
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BuildMI(MBB, I, DL, get(SystemZ::FMOV32rr), DestReg).addReg(SrcReg);
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} else if (CommonRC == &SystemZ::FP64RegClass) {
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BuildMI(MBB, I, DL, get(SystemZ::FMOV64rr), DestReg).addReg(SrcReg);
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} else {
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return false;
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}
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return true;
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}
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if ((SrcRC == &SystemZ::GR64RegClass &&
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DestRC == &SystemZ::ADDR64RegClass) ||
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(DestRC == &SystemZ::GR64RegClass &&
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SrcRC == &SystemZ::ADDR64RegClass)) {
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BuildMI(MBB, I, DL, get(SystemZ::MOV64rr), DestReg).addReg(SrcReg);
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return true;
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} else if ((SrcRC == &SystemZ::GR32RegClass &&
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DestRC == &SystemZ::ADDR32RegClass) ||
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(DestRC == &SystemZ::GR32RegClass &&
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SrcRC == &SystemZ::ADDR32RegClass)) {
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BuildMI(MBB, I, DL, get(SystemZ::MOV32rr), DestReg).addReg(SrcReg);
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return true;
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}
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return false;
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}
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bool
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SystemZInstrInfo::isMoveInstr(const MachineInstr& MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
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switch (MI.getOpcode()) {
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default:
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return false;
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case SystemZ::MOV32rr:
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case SystemZ::MOV64rr:
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case SystemZ::MOV64rrP:
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case SystemZ::MOV128rr:
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case SystemZ::FMOV32rr:
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case SystemZ::FMOV64rr:
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assert(MI.getNumOperands() >= 2 &&
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MI.getOperand(0).isReg() &&
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MI.getOperand(1).isReg() &&
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"invalid register-register move instruction");
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SrcReg = MI.getOperand(1).getReg();
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DstReg = MI.getOperand(0).getReg();
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SrcSubIdx = MI.getOperand(1).getSubReg();
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DstSubIdx = MI.getOperand(0).getSubReg();
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return true;
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}
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}
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bool
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SystemZInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI) const {
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if (CSI.empty())
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return false;
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
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unsigned CalleeFrameSize = 0;
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// Scan the callee-saved and find the bounds of register spill area.
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unsigned LowReg = 0, HighReg = 0, StartOffset = -1U, EndOffset = 0;
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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const TargetRegisterClass *RegClass = CSI[i].getRegClass();
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if (RegClass != &SystemZ::FP64RegClass) {
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unsigned Offset = RegSpillOffsets[Reg];
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CalleeFrameSize += 8;
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if (StartOffset > Offset) {
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LowReg = Reg; StartOffset = Offset;
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}
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if (EndOffset < Offset) {
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HighReg = Reg; EndOffset = RegSpillOffsets[Reg];
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}
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}
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}
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// Save information for epilogue inserter.
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MFI->setCalleeSavedFrameSize(CalleeFrameSize);
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MFI->setLowReg(LowReg); MFI->setHighReg(HighReg);
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// Save GPRs
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if (StartOffset) {
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// Build a store instruction. Use STORE MULTIPLE instruction if there are many
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// registers to store, otherwise - just STORE.
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MachineInstrBuilder MIB =
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BuildMI(MBB, MI, DL, get((LowReg == HighReg ?
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SystemZ::MOV64mr : SystemZ::MOV64mrm)));
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// Add store operands.
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MIB.addReg(SystemZ::R15D).addImm(StartOffset);
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if (LowReg == HighReg)
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MIB.addReg(0);
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MIB.addReg(LowReg, RegState::Kill);
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if (LowReg != HighReg)
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MIB.addReg(HighReg, RegState::Kill);
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// Do a second scan adding regs as being killed by instruction
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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// Add the callee-saved register as live-in. It's killed at the spill.
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MBB.addLiveIn(Reg);
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if (Reg != LowReg && Reg != HighReg)
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MIB.addReg(Reg, RegState::ImplicitKill);
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}
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}
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// Save FPRs
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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const TargetRegisterClass *RegClass = CSI[i].getRegClass();
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if (RegClass == &SystemZ::FP64RegClass) {
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MBB.addLiveIn(Reg);
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storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), RegClass);
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}
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}
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return true;
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}
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bool
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SystemZInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI) const {
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if (CSI.empty())
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return false;
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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const TargetRegisterInfo *RegInfo= MF.getTarget().getRegisterInfo();
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SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
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// Restore FP registers
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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const TargetRegisterClass *RegClass = CSI[i].getRegClass();
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if (RegClass == &SystemZ::FP64RegClass)
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loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
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}
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// Restore GP registers
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unsigned LowReg = MFI->getLowReg(), HighReg = MFI->getHighReg();
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unsigned StartOffset = RegSpillOffsets[LowReg];
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if (StartOffset) {
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// Build a load instruction. Use LOAD MULTIPLE instruction if there are many
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// registers to load, otherwise - just LOAD.
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MachineInstrBuilder MIB =
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BuildMI(MBB, MI, DL, get((LowReg == HighReg ?
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SystemZ::MOV64rm : SystemZ::MOV64rmm)));
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// Add store operands.
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MIB.addReg(LowReg, RegState::Define);
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if (LowReg != HighReg)
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MIB.addReg(HighReg, RegState::Define);
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MIB.addReg((RegInfo->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D));
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MIB.addImm(StartOffset);
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if (LowReg == HighReg)
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MIB.addReg(0);
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// Do a second scan adding regs as being defined by instruction
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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if (Reg != LowReg && Reg != HighReg)
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MIB.addReg(Reg, RegState::ImplicitDefine);
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}
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}
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return true;
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}
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unsigned
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SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const {
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// FIXME: this should probably have a DebugLoc operand
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DebugLoc dl = DebugLoc::getUnknownLoc();
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 1 || Cond.size() == 0) &&
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"SystemZ branch conditions have one component!");
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if (Cond.empty()) {
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// Unconditional branch?
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assert(!FBB && "Unconditional branch with multiple successors!");
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BuildMI(&MBB, dl, get(SystemZ::JMP)).addMBB(TBB);
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return 1;
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}
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// Conditional branch.
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unsigned Count = 0;
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SystemZCC::CondCodes CC = (SystemZCC::CondCodes)Cond[0].getImm();
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BuildMI(&MBB, dl, getBrCond(CC)).addMBB(TBB);
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++Count;
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if (FBB) {
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// Two-way Conditional branch. Insert the second branch.
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BuildMI(&MBB, dl, get(SystemZ::JMP)).addMBB(FBB);
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++Count;
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}
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return Count;
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}
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const TargetInstrDesc&
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SystemZInstrInfo::getBrCond(SystemZCC::CondCodes CC) const {
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unsigned Opc;
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switch (CC) {
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default:
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assert(0 && "Unknown condition code!");
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case SystemZCC::E:
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Opc = SystemZ::JE;
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break;
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case SystemZCC::NE:
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Opc = SystemZ::JNE;
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break;
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case SystemZCC::H:
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Opc = SystemZ::JH;
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break;
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case SystemZCC::L:
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Opc = SystemZ::JL;
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break;
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case SystemZCC::HE:
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Opc = SystemZ::JHE;
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break;
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case SystemZCC::LE:
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Opc = SystemZ::JLE;
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break;
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}
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return get(Opc);
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}
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const TargetInstrDesc&
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SystemZInstrInfo::getLongDispOpc(unsigned Opc) const {
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switch (Opc) {
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case SystemZ::MOV32mr:
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Opc = SystemZ::MOV32mry;
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break;
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case SystemZ::MOV32rm:
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Opc = SystemZ::MOV32rmy;
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break;
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case SystemZ::MOVSX32rm16:
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Opc = SystemZ::MOVSX32rm16y;
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break;
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case SystemZ::MOV32m8r:
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Opc = SystemZ::MOV32m8ry;
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break;
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case SystemZ::MOV32m16r:
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Opc = SystemZ::MOV32m16ry;
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break;
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case SystemZ::MOV64m8r:
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Opc = SystemZ::MOV64m8ry;
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break;
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case SystemZ::MOV64m16r:
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Opc = SystemZ::MOV64m16ry;
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break;
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case SystemZ::MOV64m32r:
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Opc = SystemZ::MOV64m32ry;
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break;
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case SystemZ::MOV8mi:
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Opc = SystemZ::MOV8miy;
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break;
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case SystemZ::MUL32rm:
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Opc = SystemZ::MUL32rmy;
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break;
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case SystemZ::CMP32rm:
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Opc = SystemZ::CMP32rmy;
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break;
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case SystemZ::UCMP32rm:
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Opc = SystemZ::UCMP32rmy;
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break;
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case SystemZ::FMOV32mr:
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Opc = SystemZ::FMOV32mry;
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break;
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case SystemZ::FMOV64mr:
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Opc = SystemZ::FMOV64mry;
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break;
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default:
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break;
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}
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return get(Opc);
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}
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