llvm-6502/test/CodeGen
Bruno Cardoso Lopes a0112d0c39 Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairs
to load/store i64 values. Since there's no current support to explicitly
declare such restrictions, implement it by using specific hardcoded register
pairs during isel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132248 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28 04:07:29 +00:00
..
Alpha
ARM Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairs 2011-05-28 04:07:29 +00:00
Blackfin
CBackend
CellSPU
CPP
Generic
MBlaze
Mips Define a wrapper node for target constant nodes (tglobaladdr, etc.). 2011-05-28 01:07:07 +00:00
MSP430
PowerPC
PTX
SPARC
SystemZ
Thumb
Thumb2
X86 Force a triple to make this test pass on Darwin. 2011-05-27 23:12:48 +00:00
XCore