mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86149 91177308-0d34-0410-b5e6-96231b3b80d8
498 lines
16 KiB
C++
498 lines
16 KiB
C++
//===-- MSP430ISelDAGToDAG.cpp - A dag to dag inst selector for MSP430 ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the MSP430 target.
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//
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//===----------------------------------------------------------------------===//
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#include "MSP430.h"
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#include "MSP430ISelLowering.h"
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#include "MSP430TargetMachine.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/CallingConv.h"
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#include "llvm/Constants.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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#ifndef NDEBUG
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static cl::opt<bool>
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ViewRMWDAGs("view-msp430-rmw-dags", cl::Hidden,
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cl::desc("Pop up a window to show isel dags after RMW preprocess"));
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#else
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static const bool ViewRMWDAGs = false;
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#endif
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STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
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/// MSP430DAGToDAGISel - MSP430 specific code to select MSP430 machine
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/// instructions for SelectionDAG operations.
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///
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namespace {
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class MSP430DAGToDAGISel : public SelectionDAGISel {
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MSP430TargetLowering &Lowering;
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const MSP430Subtarget &Subtarget;
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public:
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MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel)
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: SelectionDAGISel(TM, OptLevel),
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Lowering(*TM.getTargetLowering()),
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Subtarget(*TM.getSubtargetImpl()) { }
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virtual void InstructionSelect();
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virtual const char *getPassName() const {
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return "MSP430 DAG->DAG Pattern Instruction Selection";
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}
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bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
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SDNode *Root) const;
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virtual bool
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SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
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std::vector<SDValue> &OutOps);
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// Include the pieces autogenerated from the target description.
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#include "MSP430GenDAGISel.inc"
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private:
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DenseMap<SDNode*, SDNode*> RMWStores;
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void PreprocessForRMW();
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SDNode *Select(SDValue Op);
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bool SelectAddr(SDValue Op, SDValue Addr, SDValue &Base, SDValue &Disp);
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#ifndef NDEBUG
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unsigned Indent;
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#endif
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};
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} // end anonymous namespace
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/// createMSP430ISelDag - This pass converts a legalized DAG into a
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/// MSP430-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM,
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CodeGenOpt::Level OptLevel) {
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return new MSP430DAGToDAGISel(TM, OptLevel);
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}
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// FIXME: This is pretty dummy routine and needs to be rewritten in the future.
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bool MSP430DAGToDAGISel::SelectAddr(SDValue Op, SDValue Addr,
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SDValue &Base, SDValue &Disp) {
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// Try to match frame address first.
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i16);
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Disp = CurDAG->getTargetConstant(0, MVT::i16);
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return true;
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}
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switch (Addr.getOpcode()) {
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case ISD::ADD:
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// Operand is a result from ADD with constant operand which fits into i16.
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
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uint64_t CVal = CN->getZExtValue();
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// Offset should fit into 16 bits.
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if (((CVal << 48) >> 48) == CVal) {
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SDValue N0 = Addr.getOperand(0);
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N0))
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i16);
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else
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Base = N0;
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Disp = CurDAG->getTargetConstant(CVal, MVT::i16);
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return true;
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}
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}
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break;
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case MSP430ISD::Wrapper:
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SDValue N0 = Addr.getOperand(0);
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
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Base = CurDAG->getTargetGlobalAddress(G->getGlobal(),
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MVT::i16, G->getOffset());
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Disp = CurDAG->getTargetConstant(0, MVT::i16);
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return true;
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} else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(N0)) {
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Base = CurDAG->getTargetExternalSymbol(E->getSymbol(), MVT::i16);
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Disp = CurDAG->getTargetConstant(0, MVT::i16);
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}
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break;
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};
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Base = Addr;
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Disp = CurDAG->getTargetConstant(0, MVT::i16);
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return true;
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}
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bool MSP430DAGToDAGISel::
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SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
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std::vector<SDValue> &OutOps) {
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SDValue Op0, Op1;
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switch (ConstraintCode) {
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default: return true;
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case 'm': // memory
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if (!SelectAddr(Op, Op, Op0, Op1))
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return true;
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break;
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}
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OutOps.push_back(Op0);
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OutOps.push_back(Op1);
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return false;
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}
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bool MSP430DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
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SDNode *Root) const {
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if (OptLevel == CodeGenOpt::None) return false;
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/// RMW preprocessing creates the following code:
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/// [Load1]
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/// ^ ^
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/// / |
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/// / |
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/// [Load2] |
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/// ^ ^ |
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/// | | |
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/// | \-|
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/// | |
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/// | [Op]
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/// | ^
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/// | |
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/// \ /
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/// \ /
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/// [Store]
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///
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/// The path Store => Load2 => Load1 is via chain. Note that in general it is
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/// not allowed to fold Load1 into Op (and Store) since it will creates a
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/// cycle. However, this is perfectly legal for the loads moved below the
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/// TokenFactor by PreprocessForRMW. Query the map Store => Load1 (created
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/// during preprocessing) to determine whether it's legal to introduce such
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/// "cycle" for a moment.
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DenseMap<SDNode*, SDNode*>::iterator I = RMWStores.find(Root);
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if (I != RMWStores.end() && I->second == N)
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return true;
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// Proceed to 'generic' cycle finder code
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return SelectionDAGISel::IsLegalAndProfitableToFold(N, U, Root);
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}
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/// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
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/// and move load below the TokenFactor. Replace store's chain operand with
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/// load's chain result.
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static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load,
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SDValue Store, SDValue TF) {
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SmallVector<SDValue, 4> Ops;
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for (unsigned i = 0, e = TF.getNode()->getNumOperands(); i != e; ++i)
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if (Load.getNode() == TF.getOperand(i).getNode())
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Ops.push_back(Load.getOperand(0));
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else
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Ops.push_back(TF.getOperand(i));
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SDValue NewTF = CurDAG->UpdateNodeOperands(TF, &Ops[0], Ops.size());
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SDValue NewLoad = CurDAG->UpdateNodeOperands(Load, NewTF,
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Load.getOperand(1),
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Load.getOperand(2));
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CurDAG->UpdateNodeOperands(Store, NewLoad.getValue(1), Store.getOperand(1),
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Store.getOperand(2), Store.getOperand(3));
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}
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/// MoveBelowTokenFactor2 - Replace TokenFactor operand with load's chain operand
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/// and move load below the TokenFactor. Replace store's chain operand with
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/// load's chain result. This a version which sinks two loads below token factor.
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/// Look into PreprocessForRMW comments for explanation of transform.
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static void MoveBelowTokenFactor2(SelectionDAG *CurDAG,
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SDValue Load1, SDValue Load2,
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SDValue Store, SDValue TF) {
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SmallVector<SDValue, 4> Ops;
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for (unsigned i = 0, e = TF.getNode()->getNumOperands(); i != e; ++i) {
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SDNode* N = TF.getOperand(i).getNode();
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if (Load2.getNode() == N)
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Ops.push_back(Load2.getOperand(0));
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else if (Load1.getNode() != N)
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Ops.push_back(TF.getOperand(i));
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}
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SDValue NewTF = SDValue(CurDAG->MorphNodeTo(TF.getNode(),
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TF.getOpcode(),
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TF.getNode()->getVTList(),
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&Ops[0], Ops.size()), TF.getResNo());
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SDValue NewLoad2 = CurDAG->UpdateNodeOperands(Load2, NewTF,
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Load2.getOperand(1),
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Load2.getOperand(2));
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SDValue NewLoad1 = CurDAG->UpdateNodeOperands(Load1, NewLoad2.getValue(1),
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Load1.getOperand(1),
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Load1.getOperand(2));
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CurDAG->UpdateNodeOperands(Store,
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NewLoad1.getValue(1),
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Store.getOperand(1),
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Store.getOperand(2), Store.getOperand(3));
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}
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/// isAllowedToSink - return true if N a load which can be moved below token
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/// factor. Basically, the load should be non-volatile and has single use.
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static bool isLoadAllowedToSink(SDValue N, SDValue Chain) {
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if (N.getOpcode() == ISD::BIT_CONVERT)
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N = N.getOperand(0);
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LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
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if (!LD || LD->isVolatile())
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return false;
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if (LD->getAddressingMode() != ISD::UNINDEXED)
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return false;
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ISD::LoadExtType ExtType = LD->getExtensionType();
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if (ExtType != ISD::NON_EXTLOAD && ExtType != ISD::EXTLOAD)
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return false;
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return (N.hasOneUse() &&
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LD->hasNUsesOfValue(1, 1) &&
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LD->isOperandOf(Chain.getNode()));
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}
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/// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG.
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/// The chain produced by the load must only be used by the store's chain
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/// operand, otherwise this may produce a cycle in the DAG.
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static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address,
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SDValue &Load) {
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if (isLoadAllowedToSink(N, Chain) &&
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N.getOperand(1) == Address) {
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Load = N;
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return true;
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}
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return false;
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}
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/// PreprocessForRMW - Preprocess the DAG to make instruction selection better.
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/// This is only run if not in -O0 mode.
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/// This allows the instruction selector to pick more read-modify-write
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/// instructions. This is a common case:
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///
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/// [Load chain]
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/// ^
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/// |
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/// [Load]
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/// ^ ^
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/// | |
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/// / \-
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/// / |
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/// [TokenFactor] [Op]
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/// ^ ^
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/// | |
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/// \ /
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/// \ /
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/// [Store]
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///
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/// The fact the store's chain operand != load's chain will prevent the
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/// (store (op (load))) instruction from being selected. We can transform it to:
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///
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/// [Load chain]
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/// ^
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/// |
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/// [TokenFactor]
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/// ^
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/// |
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/// [Load]
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/// ^ ^
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/// | |
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/// | \-
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/// | |
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/// | [Op]
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/// | ^
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/// | |
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/// \ /
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/// \ /
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/// [Store]
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///
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/// We also recognize the case where second operand of Op is load as well and
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/// move it below token factor as well creating DAG as follows:
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///
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/// [Load chain]
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/// ^
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/// |
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/// [TokenFactor]
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/// ^
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/// |
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/// [Load1]
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/// ^ ^
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/// / |
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/// / |
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/// [Load2] |
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/// ^ ^ |
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/// | | |
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/// | \-|
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/// | |
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/// | [Op]
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/// | ^
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/// | |
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/// \ /
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/// \ /
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/// [Store]
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///
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/// This allows selection of mem-mem instructions. Yay!
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void MSP430DAGToDAGISel::PreprocessForRMW() {
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for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
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E = CurDAG->allnodes_end(); I != E; ++I) {
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if (!ISD::isNON_TRUNCStore(I))
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continue;
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SDValue Chain = I->getOperand(0);
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if (Chain.getNode()->getOpcode() != ISD::TokenFactor)
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continue;
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SDValue N1 = I->getOperand(1);
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SDValue N2 = I->getOperand(2);
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if ((N1.getValueType().isFloatingPoint() &&
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!N1.getValueType().isVector()) ||
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!N1.hasOneUse())
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continue;
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unsigned RModW = 0;
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SDValue Load1, Load2;
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unsigned Opcode = N1.getNode()->getOpcode();
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switch (Opcode) {
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case ISD::ADD:
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case ISD::AND:
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case ISD::OR:
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case ISD::XOR:
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case ISD::ADDC:
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case ISD::ADDE: {
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SDValue N10 = N1.getOperand(0);
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SDValue N11 = N1.getOperand(1);
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if (isRMWLoad(N10, Chain, N2, Load1)) {
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if (isLoadAllowedToSink(N11, Chain)) {
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Load2 = N11;
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RModW = 2;
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} else
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RModW = 1;
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} else if (isRMWLoad(N11, Chain, N2, Load1)) {
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if (isLoadAllowedToSink(N10, Chain)) {
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Load2 = N10;
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RModW = 2;
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} else
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RModW = 1;
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}
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break;
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}
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case ISD::SUB:
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case ISD::SUBC:
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case ISD::SUBE: {
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SDValue N10 = N1.getOperand(0);
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SDValue N11 = N1.getOperand(1);
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if (isRMWLoad(N10, Chain, N2, Load1)) {
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if (isLoadAllowedToSink(N11, Chain)) {
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Load2 = N11;
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RModW = 2;
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} else
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RModW = 1;
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}
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break;
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}
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}
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NumLoadMoved += RModW;
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if (RModW == 1)
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MoveBelowTokenFactor(CurDAG, Load1, SDValue(I, 0), Chain);
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else if (RModW == 2) {
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MoveBelowTokenFactor2(CurDAG, Load1, Load2, SDValue(I, 0), Chain);
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SDNode* Store = I;
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RMWStores[Store] = Load2.getNode();
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}
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}
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}
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/// InstructionSelect - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void MSP430DAGToDAGISel::InstructionSelect() {
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std::string BlockName;
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if (ViewRMWDAGs)
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BlockName = MF->getFunction()->getNameStr() + ":" +
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BB->getBasicBlock()->getNameStr();
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PreprocessForRMW();
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if (ViewRMWDAGs) CurDAG->viewGraph("RMW preprocessed:" + BlockName);
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DEBUG(errs() << "Selection DAG after RMW preprocessing:\n");
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DEBUG(CurDAG->dump());
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// Codegen the basic block.
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DEBUG(errs() << "===== Instruction selection begins:\n");
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DEBUG(Indent = 0);
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SelectRoot(*CurDAG);
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DEBUG(errs() << "===== Instruction selection ends:\n");
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CurDAG->RemoveDeadNodes();
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RMWStores.clear();
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}
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SDNode *MSP430DAGToDAGISel::Select(SDValue Op) {
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SDNode *Node = Op.getNode();
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DebugLoc dl = Op.getDebugLoc();
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// Dump information about the Node being selected
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DEBUG(errs().indent(Indent) << "Selecting: ");
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DEBUG(Node->dump(CurDAG));
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DEBUG(errs() << "\n");
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DEBUG(Indent += 2);
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// If we have a custom node, we already have selected!
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if (Node->isMachineOpcode()) {
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DEBUG(errs().indent(Indent-2) << "== ";
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Node->dump(CurDAG);
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errs() << "\n");
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DEBUG(Indent -= 2);
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return NULL;
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}
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// Few custom selection stuff.
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switch (Node->getOpcode()) {
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default: break;
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case ISD::FrameIndex: {
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assert(Op.getValueType() == MVT::i16);
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int FI = cast<FrameIndexSDNode>(Node)->getIndex();
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SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i16);
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if (Node->hasOneUse())
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return CurDAG->SelectNodeTo(Node, MSP430::ADD16ri, MVT::i16,
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TFI, CurDAG->getTargetConstant(0, MVT::i16));
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return CurDAG->getMachineNode(MSP430::ADD16ri, dl, MVT::i16,
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TFI, CurDAG->getTargetConstant(0, MVT::i16));
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}
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}
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// Select the default instruction
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SDNode *ResNode = SelectCode(Op);
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DEBUG(errs() << std::string(Indent-2, ' ') << "=> ");
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if (ResNode == NULL || ResNode == Op.getNode())
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DEBUG(Op.getNode()->dump(CurDAG));
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else
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DEBUG(ResNode->dump(CurDAG));
|
|
DEBUG(errs() << "\n");
|
|
DEBUG(Indent -= 2);
|
|
|
|
return ResNode;
|
|
}
|