Daniel Sanders b6d2c5a952 [mips] Correct 128-bit shifts on 64-bit targets. ... Summary: The existing code was correct for 32-bit GPR's but not 64-bit GPR's. It now accounts for both cases. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits, mohit.bhakkad, sagar Differential Revision: http://reviews.llvm.org/D9337 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236099 91177308-0d34-0410-b5e6-96231b3b80d8		2015-04-29 12:28:58 +00:00
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AArch64	[AArch64] Also combine vector selects fed by non-i1 SETCCs.	2015-04-27 21:43:12 +00:00
ARM	ARM: fix peephole optimisation of TST	2015-04-28 22:03:55 +00:00
BPF
CPP
Generic	Switch lowering: Take branch weight into account when ordering for fall-through	2015-04-27 23:35:22 +00:00
Hexagon	[Hexagon] Use constant extenders to fix up hardware loops	2015-04-27 14:16:43 +00:00
Inputs
Mips	[mips] Correct 128-bit shifts on 64-bit targets.	2015-04-29 12:28:58 +00:00
MSP430
NVPTX	[NVPTX] Handle addrspacecast constant expressions in aggregate initializers	2015-04-28 17:18:30 +00:00
PowerPC	[PPC64LE] Remove unnecessary swaps from lane-insensitive vector computations	2015-04-27 19:57:34 +00:00
R600	R600: Fix up for AsmPrinter's OutStreamer being a unique_ptr	2015-04-28 17:37:03 +00:00
SPARC
SystemZ
Thumb
Thumb2	Thumb2: When applying branch optimizations, visit branches in reverse order.	2015-04-23 20:31:35 +00:00
WinEH	[WinEH] Split blocks at calls to llvm.eh.begincatch	2015-04-28 21:54:14 +00:00
X86	transform fadd chains to increase parallelism	2015-04-28 21:03:22 +00:00
XCore