1
0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-29 10:32:47 +00:00
llvm-6502/lib/CodeGen/SelectionDAG
Dan Gohman b6f5b00c3b Add new TargetLowering code to provide the final register type that an
illegal value type will be transformed to, for code that needs the
register type after all transformations instead of just after the first
transformation.

Factor out the code that uses this information to do copy-from-regs and
copy-to-regs for various purposes into separate functions so that they
are done consistently.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37781 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-28 23:29:44 +00:00
..
CallingConvLower.cpp add isVarArg to CCState 2007-06-19 00:11:09 +00:00
DAGCombiner.cpp Generalize MVT::ValueType and associated functions to be able to represent 2007-06-25 16:23:39 +00:00
LegalizeDAG.cpp Rename ("shrinkify") MVT::isExtendedValueType to MVT::isExtendedVT. 2007-06-27 16:08:04 +00:00
Makefile
ScheduleDAG.cpp Pass a SelectionDAG into SDNode::dump everywhere it's used, in prepration 2007-06-19 14:13:56 +00:00
ScheduleDAGList.cpp
ScheduleDAGRRList.cpp std::set is really really terrible. Switch to SmallPtrSet to reduce compile time. For Duraid's example. The overall isel time is reduced from 0.6255 sec to 0.1876 sec. 2007-06-22 01:35:51 +00:00
ScheduleDAGSimple.cpp
SelectionDAG.cpp Rename ("shrinkify") MVT::isExtendedValueType to MVT::isExtendedVT. 2007-06-27 16:08:04 +00:00
SelectionDAGISel.cpp Add new TargetLowering code to provide the final register type that an 2007-06-28 23:29:44 +00:00
SelectionDAGPrinter.cpp
TargetLowering.cpp Add new TargetLowering code to provide the final register type that an 2007-06-28 23:29:44 +00:00