NAKAMURA Takumi b720a3d15c Re-apply r211399, "Generate native unwind info on Win64" with a fix to ignore SEH pseudo ops in X86 JIT emitter. ... -- This patch enables LLVM to emit Win64-native unwind info rather than DWARF CFI. It handles all corner cases (I hope), including stack realignment. Because the unwind info is not flexible enough to describe stack frames with a gap of unknown size in the middle, such as the one caused by stack realignment, I modified register spilling code to place all spills into the fixed frame slots, so that they can be accessed relative to the frame pointer. Patch by Vadim Chugunov! Reviewed By: rnk Differential Revision: http://reviews.llvm.org/D4081 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211691 91177308-0d34-0410-b5e6-96231b3b80d8		2014-06-25 12:41:52 +00:00
..
AArch64	Resubmit commit r211533	2014-06-24 16:21:38 +00:00
ARM	Fix up scoping in a few tests (and delete one that validates unnecessary behavior).	2014-06-24 20:10:27 +00:00
CPP	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
Generic
Hexagon
Inputs
Mips	Print a=b as an assignment.	2014-06-24 22:45:16 +00:00
MSP430
NVPTX	Canonicalize addrspacecast ConstExpr between different pointer types	2014-06-15 21:40:57 +00:00
PowerPC	[PPC64] Fix PR20071 (fctiduz generated for targets lacking that instruction)	2014-06-24 20:05:18 +00:00
R600	R600: Promote i64 stores to v2i32	2014-06-24 23:33:04 +00:00
SPARC	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
SystemZ	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
Thumb
Thumb2	ARM: Fix TPsoft for Thumb mode	2014-06-24 15:45:59 +00:00
X86	Re-apply r211399, "Generate native unwind info on Win64" with a fix to ignore SEH pseudo ops in X86 JIT emitter.	2014-06-25 12:41:52 +00:00
XCore