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By definition copies across register banks are not coalescable. Still, it may be possible to get rid of such a copy when the value is available in another register of the same register file. Consider the following example, where capital and lower letters denote different register file: b = copy A <-- cross-bank copy ... C = copy b <-- cross-bank copy This could have been optimized this way: b = copy A <-- cross-bank copy ... C = copy A <-- same-bank copy Note: b and C's definitions may be in different basic blocks. This patch adds a peephole optimization that looks through a chain of copies leading to a cross-bank copy and reuses a source that is on the same register file if available. This solution could also be used to get rid of some copies (e.g., A could have been used instead of C). However, we do not do so because: - It may over constrain the coloring of the source register for coalescing. - The register allocator may not be able to find a nice split point for the longer live-range, leading to more spill. <rdar://problem/14742333> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190713 91177308-0d34-0410-b5e6-96231b3b80d8
660 lines
24 KiB
C++
660 lines
24 KiB
C++
//===-- PeepholeOptimizer.cpp - Peephole Optimizations --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Perform peephole optimizations on the machine code:
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//
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// - Optimize Extensions
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//
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// Optimization of sign / zero extension instructions. It may be extended to
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// handle other instructions with similar properties.
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//
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// On some targets, some instructions, e.g. X86 sign / zero extension, may
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// leave the source value in the lower part of the result. This optimization
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// will replace some uses of the pre-extension value with uses of the
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// sub-register of the results.
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//
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// - Optimize Comparisons
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//
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// Optimization of comparison instructions. For instance, in this code:
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//
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// sub r1, 1
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// cmp r1, 0
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// bz L1
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//
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// If the "sub" instruction all ready sets (or could be modified to set) the
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// same flag that the "cmp" instruction sets and that "bz" uses, then we can
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// eliminate the "cmp" instruction.
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//
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// Another instance, in this code:
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//
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// sub r1, r3 | sub r1, imm
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// cmp r3, r1 or cmp r1, r3 | cmp r1, imm
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// bge L1
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//
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// If the branch instruction can use flag from "sub", then we can replace
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// "sub" with "subs" and eliminate the "cmp" instruction.
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//
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// - Optimize Loads:
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//
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// Loads that can be folded into a later instruction. A load is foldable
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// if it loads to virtual registers and the virtual register defined has
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// a single use.
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//
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// - Optimize Copies and Bitcast:
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//
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// Rewrite copies and bitcasts to avoid cross register bank copies
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// when possible.
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// E.g., Consider the following example, where capital and lower
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// letters denote different register file:
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// b = copy A <-- cross-bank copy
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// C = copy b <-- cross-bank copy
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// =>
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// b = copy A <-- cross-bank copy
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// C = copy A <-- same-bank copy
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//
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// E.g., for bitcast:
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// b = bitcast A <-- cross-bank copy
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// C = bitcast b <-- cross-bank copy
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// =>
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// b = bitcast A <-- cross-bank copy
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// C = copy A <-- same-bank copy
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "peephole-opt"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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// Optimize Extensions
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static cl::opt<bool>
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Aggressive("aggressive-ext-opt", cl::Hidden,
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cl::desc("Aggressive extension optimization"));
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static cl::opt<bool>
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DisablePeephole("disable-peephole", cl::Hidden, cl::init(false),
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cl::desc("Disable the peephole optimizer"));
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STATISTIC(NumReuse, "Number of extension results reused");
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STATISTIC(NumCmps, "Number of compares eliminated");
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STATISTIC(NumImmFold, "Number of move immediate folded");
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STATISTIC(NumLoadFold, "Number of loads folded");
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STATISTIC(NumSelects, "Number of selects optimized");
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STATISTIC(NumCopiesBitcasts, "Number of copies/bitcasts optimized");
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namespace {
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class PeepholeOptimizer : public MachineFunctionPass {
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const TargetMachine *TM;
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const TargetInstrInfo *TII;
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MachineRegisterInfo *MRI;
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MachineDominatorTree *DT; // Machine dominator tree
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public:
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static char ID; // Pass identification
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PeepholeOptimizer() : MachineFunctionPass(ID) {
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initializePeepholeOptimizerPass(*PassRegistry::getPassRegistry());
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}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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if (Aggressive) {
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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}
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}
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private:
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bool optimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB);
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bool optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
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SmallPtrSet<MachineInstr*, 8> &LocalMIs);
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bool optimizeSelect(MachineInstr *MI);
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bool optimizeCopyOrBitcast(MachineInstr *MI);
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bool isMoveImmediate(MachineInstr *MI,
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SmallSet<unsigned, 4> &ImmDefRegs,
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DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
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bool foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB,
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SmallSet<unsigned, 4> &ImmDefRegs,
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DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
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bool isLoadFoldable(MachineInstr *MI, unsigned &FoldAsLoadDefReg);
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};
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}
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char PeepholeOptimizer::ID = 0;
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char &llvm::PeepholeOptimizerID = PeepholeOptimizer::ID;
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INITIALIZE_PASS_BEGIN(PeepholeOptimizer, "peephole-opts",
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"Peephole Optimizations", false, false)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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INITIALIZE_PASS_END(PeepholeOptimizer, "peephole-opts",
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"Peephole Optimizations", false, false)
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/// optimizeExtInstr - If instruction is a copy-like instruction, i.e. it reads
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/// a single register and writes a single register and it does not modify the
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/// source, and if the source value is preserved as a sub-register of the
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/// result, then replace all reachable uses of the source with the subreg of the
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/// result.
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///
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/// Do not generate an EXTRACT that is used only in a debug use, as this changes
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/// the code. Since this code does not currently share EXTRACTs, just ignore all
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/// debug uses.
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bool PeepholeOptimizer::
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optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
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SmallPtrSet<MachineInstr*, 8> &LocalMIs) {
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unsigned SrcReg, DstReg, SubIdx;
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if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
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return false;
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if (TargetRegisterInfo::isPhysicalRegister(DstReg) ||
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TargetRegisterInfo::isPhysicalRegister(SrcReg))
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return false;
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if (MRI->hasOneNonDBGUse(SrcReg))
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// No other uses.
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return false;
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// Ensure DstReg can get a register class that actually supports
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// sub-registers. Don't change the class until we commit.
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const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
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DstRC = TM->getRegisterInfo()->getSubClassWithSubReg(DstRC, SubIdx);
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if (!DstRC)
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return false;
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// The ext instr may be operating on a sub-register of SrcReg as well.
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// PPC::EXTSW is a 32 -> 64-bit sign extension, but it reads a 64-bit
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// register.
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// If UseSrcSubIdx is Set, SubIdx also applies to SrcReg, and only uses of
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// SrcReg:SubIdx should be replaced.
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bool UseSrcSubIdx = TM->getRegisterInfo()->
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getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != 0;
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// The source has other uses. See if we can replace the other uses with use of
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// the result of the extension.
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SmallPtrSet<MachineBasicBlock*, 4> ReachedBBs;
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for (MachineRegisterInfo::use_nodbg_iterator
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UI = MRI->use_nodbg_begin(DstReg), UE = MRI->use_nodbg_end();
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UI != UE; ++UI)
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ReachedBBs.insert(UI->getParent());
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// Uses that are in the same BB of uses of the result of the instruction.
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SmallVector<MachineOperand*, 8> Uses;
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// Uses that the result of the instruction can reach.
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SmallVector<MachineOperand*, 8> ExtendedUses;
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bool ExtendLife = true;
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for (MachineRegisterInfo::use_nodbg_iterator
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UI = MRI->use_nodbg_begin(SrcReg), UE = MRI->use_nodbg_end();
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UI != UE; ++UI) {
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MachineOperand &UseMO = UI.getOperand();
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MachineInstr *UseMI = &*UI;
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if (UseMI == MI)
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continue;
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if (UseMI->isPHI()) {
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ExtendLife = false;
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continue;
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}
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// Only accept uses of SrcReg:SubIdx.
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if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx)
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continue;
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// It's an error to translate this:
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//
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// %reg1025 = <sext> %reg1024
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// ...
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// %reg1026 = SUBREG_TO_REG 0, %reg1024, 4
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//
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// into this:
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//
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// %reg1025 = <sext> %reg1024
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// ...
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// %reg1027 = COPY %reg1025:4
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// %reg1026 = SUBREG_TO_REG 0, %reg1027, 4
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//
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// The problem here is that SUBREG_TO_REG is there to assert that an
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// implicit zext occurs. It doesn't insert a zext instruction. If we allow
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// the COPY here, it will give us the value after the <sext>, not the
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// original value of %reg1024 before <sext>.
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if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
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continue;
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MachineBasicBlock *UseMBB = UseMI->getParent();
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if (UseMBB == MBB) {
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// Local uses that come after the extension.
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if (!LocalMIs.count(UseMI))
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Uses.push_back(&UseMO);
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} else if (ReachedBBs.count(UseMBB)) {
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// Non-local uses where the result of the extension is used. Always
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// replace these unless it's a PHI.
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Uses.push_back(&UseMO);
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} else if (Aggressive && DT->dominates(MBB, UseMBB)) {
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// We may want to extend the live range of the extension result in order
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// to replace these uses.
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ExtendedUses.push_back(&UseMO);
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} else {
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// Both will be live out of the def MBB anyway. Don't extend live range of
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// the extension result.
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ExtendLife = false;
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break;
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}
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}
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if (ExtendLife && !ExtendedUses.empty())
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// Extend the liveness of the extension result.
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std::copy(ExtendedUses.begin(), ExtendedUses.end(),
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std::back_inserter(Uses));
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// Now replace all uses.
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bool Changed = false;
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if (!Uses.empty()) {
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SmallPtrSet<MachineBasicBlock*, 4> PHIBBs;
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// Look for PHI uses of the extended result, we don't want to extend the
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// liveness of a PHI input. It breaks all kinds of assumptions down
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// stream. A PHI use is expected to be the kill of its source values.
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for (MachineRegisterInfo::use_nodbg_iterator
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UI = MRI->use_nodbg_begin(DstReg), UE = MRI->use_nodbg_end();
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UI != UE; ++UI)
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if (UI->isPHI())
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PHIBBs.insert(UI->getParent());
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const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
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for (unsigned i = 0, e = Uses.size(); i != e; ++i) {
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MachineOperand *UseMO = Uses[i];
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MachineInstr *UseMI = UseMO->getParent();
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MachineBasicBlock *UseMBB = UseMI->getParent();
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if (PHIBBs.count(UseMBB))
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continue;
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// About to add uses of DstReg, clear DstReg's kill flags.
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if (!Changed) {
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MRI->clearKillFlags(DstReg);
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MRI->constrainRegClass(DstReg, DstRC);
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}
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unsigned NewVR = MRI->createVirtualRegister(RC);
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MachineInstr *Copy = BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
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TII->get(TargetOpcode::COPY), NewVR)
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.addReg(DstReg, 0, SubIdx);
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// SubIdx applies to both SrcReg and DstReg when UseSrcSubIdx is set.
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if (UseSrcSubIdx) {
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Copy->getOperand(0).setSubReg(SubIdx);
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Copy->getOperand(0).setIsUndef();
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}
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UseMO->setReg(NewVR);
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++NumReuse;
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Changed = true;
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}
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}
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return Changed;
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}
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/// optimizeCmpInstr - If the instruction is a compare and the previous
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/// instruction it's comparing against all ready sets (or could be modified to
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/// set) the same flag as the compare, then we can remove the comparison and use
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/// the flag from the previous instruction.
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bool PeepholeOptimizer::optimizeCmpInstr(MachineInstr *MI,
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MachineBasicBlock *MBB) {
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// If this instruction is a comparison against zero and isn't comparing a
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// physical register, we can try to optimize it.
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unsigned SrcReg, SrcReg2;
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int CmpMask, CmpValue;
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if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
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TargetRegisterInfo::isPhysicalRegister(SrcReg) ||
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(SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2)))
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return false;
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// Attempt to optimize the comparison instruction.
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if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
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++NumCmps;
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return true;
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}
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return false;
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}
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/// Optimize a select instruction.
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bool PeepholeOptimizer::optimizeSelect(MachineInstr *MI) {
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unsigned TrueOp = 0;
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unsigned FalseOp = 0;
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bool Optimizable = false;
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SmallVector<MachineOperand, 4> Cond;
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if (TII->analyzeSelect(MI, Cond, TrueOp, FalseOp, Optimizable))
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return false;
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if (!Optimizable)
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return false;
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if (!TII->optimizeSelect(MI))
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return false;
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MI->eraseFromParent();
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++NumSelects;
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return true;
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}
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/// \brief Check if the registers defined by the pair (RegisterClass, SubReg)
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/// share the same register file.
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static bool shareSameRegisterFile(const TargetRegisterInfo &TRI,
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const TargetRegisterClass *DefRC,
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unsigned DefSubReg,
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const TargetRegisterClass *SrcRC,
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unsigned SrcSubReg) {
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// Same register class.
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if (DefRC == SrcRC)
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return true;
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// Both operands are sub registers. Check if they share a register class.
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unsigned SrcIdx, DefIdx;
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if (SrcSubReg && DefSubReg)
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return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
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SrcIdx, DefIdx) != NULL;
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// At most one of the register is a sub register, make it Src to avoid
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// duplicating the test.
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if (!SrcSubReg) {
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std::swap(DefSubReg, SrcSubReg);
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std::swap(DefRC, SrcRC);
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}
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// One of the register is a sub register, check if we can get a superclass.
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if (SrcSubReg)
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return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != NULL;
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// Plain copy.
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return TRI.getCommonSubClass(DefRC, SrcRC) != NULL;
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}
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/// \brief Get the index of the definition and source for \p Copy
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/// instruction.
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/// \pre Copy.isCopy() or Copy.isBitcast().
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/// \return True if the Copy instruction has only one register source
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/// and one register definition. Otherwise, \p DefIdx and \p SrcIdx
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/// are invalid.
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static bool getCopyOrBitcastDefUseIdx(const MachineInstr &Copy,
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unsigned &DefIdx, unsigned &SrcIdx) {
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assert((Copy.isCopy() || Copy.isBitcast()) && "Wrong operation type.");
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if (Copy.isCopy()) {
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// Copy instruction are supposed to be: Def = Src.
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if (Copy.getDesc().getNumOperands() != 2)
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return false;
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DefIdx = 0;
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SrcIdx = 1;
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assert(Copy.getOperand(DefIdx).isDef() && "Use comes before def!");
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return true;
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}
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// Bitcast case.
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// Bitcasts with more than one def are not supported.
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if (Copy.getDesc().getNumDefs() != 1)
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return false;
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// Initialize SrcIdx to an undefined operand.
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SrcIdx = Copy.getDesc().getNumOperands();
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for (unsigned OpIdx = 0, EndOpIdx = SrcIdx; OpIdx != EndOpIdx; ++OpIdx) {
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const MachineOperand &MO = Copy.getOperand(OpIdx);
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if (!MO.isReg() || !MO.getReg())
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continue;
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if (MO.isDef())
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DefIdx = OpIdx;
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else if (SrcIdx != EndOpIdx)
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// Multiple sources?
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return false;
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SrcIdx = OpIdx;
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}
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return true;
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}
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/// \brief Optimize a copy or bitcast instruction to avoid cross
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/// register bank copy. The optimization looks through a chain of
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/// copies and try to find a source that has a compatible register
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/// class.
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/// Two register classes are considered to be compatible if they share
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/// the same register bank.
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/// New copies issued by this optimization are register allocator
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/// friendly. This optimization does not remove any copy as it may
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/// overconstraint the register allocator, but replaces some when
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/// possible.
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/// \pre \p MI is a Copy (MI->isCopy() is true)
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/// \return True, when \p MI has been optimized. In that case, \p MI has
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/// been removed from its parent.
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bool PeepholeOptimizer::optimizeCopyOrBitcast(MachineInstr *MI) {
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unsigned DefIdx, SrcIdx;
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if (!MI || !getCopyOrBitcastDefUseIdx(*MI, DefIdx, SrcIdx))
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return false;
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const MachineOperand &MODef = MI->getOperand(DefIdx);
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assert(MODef.isReg() && "Copies must be between registers.");
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unsigned Def = MODef.getReg();
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if (TargetRegisterInfo::isPhysicalRegister(Def))
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return false;
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const TargetRegisterClass *DefRC = MRI->getRegClass(Def);
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unsigned DefSubReg = MODef.getSubReg();
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unsigned Src;
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unsigned SrcSubReg;
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bool ShouldRewrite = false;
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MachineInstr *Copy = MI;
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const TargetRegisterInfo &TRI = *TM->getRegisterInfo();
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// Follow the chain of copies until we reach the top or find a
|
|
// more suitable source.
|
|
do {
|
|
unsigned CopyDefIdx, CopySrcIdx;
|
|
if (!getCopyOrBitcastDefUseIdx(*Copy, CopyDefIdx, CopySrcIdx))
|
|
break;
|
|
const MachineOperand &MO = Copy->getOperand(CopySrcIdx);
|
|
assert(MO.isReg() && "Copies must be between registers.");
|
|
Src = MO.getReg();
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(Src))
|
|
break;
|
|
|
|
const TargetRegisterClass *SrcRC = MRI->getRegClass(Src);
|
|
SrcSubReg = MO.getSubReg();
|
|
|
|
// If this source does not incur a cross register bank copy, use it.
|
|
ShouldRewrite = shareSameRegisterFile(TRI, DefRC, DefSubReg, SrcRC,
|
|
SrcSubReg);
|
|
// Follow the chain of copies: get the definition of Src.
|
|
Copy = MRI->getVRegDef(Src);
|
|
} while (!ShouldRewrite && Copy && (Copy->isCopy() || Copy->isBitcast()));
|
|
|
|
// If we did not find a more suitable source, there is nothing to optimize.
|
|
if (!ShouldRewrite || Src == MI->getOperand(SrcIdx).getReg())
|
|
return false;
|
|
|
|
// Rewrite the copy to avoid a cross register bank penalty.
|
|
unsigned NewVR = TargetRegisterInfo::isPhysicalRegister(Def) ? Def :
|
|
MRI->createVirtualRegister(DefRC);
|
|
MachineInstr *NewCopy = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
|
|
TII->get(TargetOpcode::COPY), NewVR)
|
|
.addReg(Src, 0, SrcSubReg);
|
|
NewCopy->getOperand(0).setSubReg(DefSubReg);
|
|
|
|
MRI->replaceRegWith(Def, NewVR);
|
|
MRI->clearKillFlags(NewVR);
|
|
MI->eraseFromParent();
|
|
++NumCopiesBitcasts;
|
|
return true;
|
|
}
|
|
|
|
/// isLoadFoldable - Check whether MI is a candidate for folding into a later
|
|
/// instruction. We only fold loads to virtual registers and the virtual
|
|
/// register defined has a single use.
|
|
bool PeepholeOptimizer::isLoadFoldable(MachineInstr *MI,
|
|
unsigned &FoldAsLoadDefReg) {
|
|
if (!MI->canFoldAsLoad() || !MI->mayLoad())
|
|
return false;
|
|
const MCInstrDesc &MCID = MI->getDesc();
|
|
if (MCID.getNumDefs() != 1)
|
|
return false;
|
|
|
|
unsigned Reg = MI->getOperand(0).getReg();
|
|
// To reduce compilation time, we check MRI->hasOneUse when inserting
|
|
// loads. It should be checked when processing uses of the load, since
|
|
// uses can be removed during peephole.
|
|
if (!MI->getOperand(0).getSubReg() &&
|
|
TargetRegisterInfo::isVirtualRegister(Reg) &&
|
|
MRI->hasOneUse(Reg)) {
|
|
FoldAsLoadDefReg = Reg;
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool PeepholeOptimizer::isMoveImmediate(MachineInstr *MI,
|
|
SmallSet<unsigned, 4> &ImmDefRegs,
|
|
DenseMap<unsigned, MachineInstr*> &ImmDefMIs) {
|
|
const MCInstrDesc &MCID = MI->getDesc();
|
|
if (!MI->isMoveImmediate())
|
|
return false;
|
|
if (MCID.getNumDefs() != 1)
|
|
return false;
|
|
unsigned Reg = MI->getOperand(0).getReg();
|
|
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
|
|
ImmDefMIs.insert(std::make_pair(Reg, MI));
|
|
ImmDefRegs.insert(Reg);
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
/// foldImmediate - Try folding register operands that are defined by move
|
|
/// immediate instructions, i.e. a trivial constant folding optimization, if
|
|
/// and only if the def and use are in the same BB.
|
|
bool PeepholeOptimizer::foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB,
|
|
SmallSet<unsigned, 4> &ImmDefRegs,
|
|
DenseMap<unsigned, MachineInstr*> &ImmDefMIs) {
|
|
for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg() || MO.isDef())
|
|
continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (!TargetRegisterInfo::isVirtualRegister(Reg))
|
|
continue;
|
|
if (ImmDefRegs.count(Reg) == 0)
|
|
continue;
|
|
DenseMap<unsigned, MachineInstr*>::iterator II = ImmDefMIs.find(Reg);
|
|
assert(II != ImmDefMIs.end());
|
|
if (TII->FoldImmediate(MI, II->second, Reg, MRI)) {
|
|
++NumImmFold;
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
|
|
DEBUG(dbgs() << "********** PEEPHOLE OPTIMIZER **********\n");
|
|
DEBUG(dbgs() << "********** Function: " << MF.getName() << '\n');
|
|
|
|
if (DisablePeephole)
|
|
return false;
|
|
|
|
TM = &MF.getTarget();
|
|
TII = TM->getInstrInfo();
|
|
MRI = &MF.getRegInfo();
|
|
DT = Aggressive ? &getAnalysis<MachineDominatorTree>() : 0;
|
|
|
|
bool Changed = false;
|
|
|
|
SmallPtrSet<MachineInstr*, 8> LocalMIs;
|
|
SmallSet<unsigned, 4> ImmDefRegs;
|
|
DenseMap<unsigned, MachineInstr*> ImmDefMIs;
|
|
unsigned FoldAsLoadDefReg;
|
|
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
|
|
MachineBasicBlock *MBB = &*I;
|
|
|
|
bool SeenMoveImm = false;
|
|
LocalMIs.clear();
|
|
ImmDefRegs.clear();
|
|
ImmDefMIs.clear();
|
|
FoldAsLoadDefReg = 0;
|
|
|
|
for (MachineBasicBlock::iterator
|
|
MII = I->begin(), MIE = I->end(); MII != MIE; ) {
|
|
MachineInstr *MI = &*MII;
|
|
// We may be erasing MI below, increment MII now.
|
|
++MII;
|
|
LocalMIs.insert(MI);
|
|
|
|
// If there exists an instruction which belongs to the following
|
|
// categories, we will discard the load candidate.
|
|
if (MI->isLabel() || MI->isPHI() || MI->isImplicitDef() ||
|
|
MI->isKill() || MI->isInlineAsm() || MI->isDebugValue() ||
|
|
MI->hasUnmodeledSideEffects()) {
|
|
FoldAsLoadDefReg = 0;
|
|
continue;
|
|
}
|
|
if (MI->mayStore() || MI->isCall())
|
|
FoldAsLoadDefReg = 0;
|
|
|
|
if (((MI->isBitcast() || MI->isCopy()) && optimizeCopyOrBitcast(MI)) ||
|
|
(MI->isCompare() && optimizeCmpInstr(MI, MBB)) ||
|
|
(MI->isSelect() && optimizeSelect(MI))) {
|
|
// MI is deleted.
|
|
LocalMIs.erase(MI);
|
|
Changed = true;
|
|
continue;
|
|
}
|
|
|
|
if (isMoveImmediate(MI, ImmDefRegs, ImmDefMIs)) {
|
|
SeenMoveImm = true;
|
|
} else {
|
|
Changed |= optimizeExtInstr(MI, MBB, LocalMIs);
|
|
// optimizeExtInstr might have created new instructions after MI
|
|
// and before the already incremented MII. Adjust MII so that the
|
|
// next iteration sees the new instructions.
|
|
MII = MI;
|
|
++MII;
|
|
if (SeenMoveImm)
|
|
Changed |= foldImmediate(MI, MBB, ImmDefRegs, ImmDefMIs);
|
|
}
|
|
|
|
// Check whether MI is a load candidate for folding into a later
|
|
// instruction. If MI is not a candidate, check whether we can fold an
|
|
// earlier load into MI.
|
|
if (!isLoadFoldable(MI, FoldAsLoadDefReg) && FoldAsLoadDefReg) {
|
|
// We need to fold load after optimizeCmpInstr, since optimizeCmpInstr
|
|
// can enable folding by converting SUB to CMP.
|
|
MachineInstr *DefMI = 0;
|
|
MachineInstr *FoldMI = TII->optimizeLoadInstr(MI, MRI,
|
|
FoldAsLoadDefReg, DefMI);
|
|
if (FoldMI) {
|
|
// Update LocalMIs since we replaced MI with FoldMI and deleted DefMI.
|
|
DEBUG(dbgs() << "Replacing: " << *MI);
|
|
DEBUG(dbgs() << " With: " << *FoldMI);
|
|
LocalMIs.erase(MI);
|
|
LocalMIs.erase(DefMI);
|
|
LocalMIs.insert(FoldMI);
|
|
MI->eraseFromParent();
|
|
DefMI->eraseFromParent();
|
|
++NumLoadFold;
|
|
|
|
// MI is replaced with FoldMI.
|
|
Changed = true;
|
|
continue;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return Changed;
|
|
}
|