mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-17 03:30:28 +00:00
ddf89566a9
1. Legalize now always promotes truncstore of i1 to i8. 2. Remove patterns and gunk related to truncstore i1 from targets. 3. Rename the StoreXAction stuff to TruncStoreAction in TLI. 4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions. 5. Mark a wide variety of invalid truncstores as such in various targets, e.g. X86 currently doesn't support truncstore of any of its integer types. 6. Add legalize support for truncstores with invalid value input types. 7. Add a dag combine transform to turn store(truncate) into truncstore when safe. The later allows us to compile CodeGen/X86/storetrunc-fp.ll to: _foo: fldt 20(%esp) fldt 4(%esp) faddp %st(1) movl 36(%esp), %eax fstps (%eax) ret instead of: _foo: subl $4, %esp fldt 24(%esp) fldt 8(%esp) faddp %st(1) fstps (%esp) movl 40(%esp), %eax movss (%esp), %xmm0 movss %xmm0, (%eax) addl $4, %esp ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46140 91177308-0d34-0410-b5e6-96231b3b80d8
600 lines
22 KiB
TableGen
600 lines
22 KiB
TableGen
//===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Thumb instruction set.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Thumb specific DAG Nodes.
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//
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def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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// TI - Thumb instruction.
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// ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
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class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
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list<Predicate> Predicates = [IsThumb];
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}
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class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
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list<Predicate> Predicates = [IsThumb, HasV5T];
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}
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class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
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string asm, string cstr, list<dag> pattern>
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// FIXME: Set all opcodes to 0 for now.
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: InstARM<0, am, sz, IndexModeNone, ThumbFrm, cstr> {
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let OutOperandList = outs;
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let InOperandList = ins;
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let AsmString = asm;
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let Pattern = pattern;
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list<Predicate> Predicates = [IsThumb];
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}
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class TI<dag outs, dag ins, string asm, list<dag> pattern>
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: ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>;
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class TI1<dag outs, dag ins, string asm, list<dag> pattern>
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: ThumbI<outs, ins, AddrModeT1, Size2Bytes, asm, "", pattern>;
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class TI2<dag outs, dag ins, string asm, list<dag> pattern>
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: ThumbI<outs, ins, AddrModeT2, Size2Bytes, asm, "", pattern>;
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class TI4<dag outs, dag ins, string asm, list<dag> pattern>
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: ThumbI<outs, ins, AddrModeT4, Size2Bytes, asm, "", pattern>;
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class TIs<dag outs, dag ins, string asm, list<dag> pattern>
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: ThumbI<outs, ins, AddrModeTs, Size2Bytes, asm, "", pattern>;
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// Two-address instructions
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class TIt<dag outs, dag ins, string asm, list<dag> pattern>
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: ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
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// BL, BLX(1) are translated by assembler into two instructions
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class TIx2<dag outs, dag ins, string asm, list<dag> pattern>
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: ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>;
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// BR_JT instructions
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class TJTI<dag outs, dag ins, string asm, list<dag> pattern>
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: ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>;
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def imm_neg_XFORM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(-(int)N->getValue(), MVT::i32);
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}]>;
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def imm_comp_XFORM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(~((uint32_t)N->getValue()), MVT::i32);
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}]>;
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/// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
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def imm0_7 : PatLeaf<(i32 imm), [{
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return (uint32_t)N->getValue() < 8;
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}]>;
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def imm0_7_neg : PatLeaf<(i32 imm), [{
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return (uint32_t)-N->getValue() < 8;
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}], imm_neg_XFORM>;
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def imm0_255 : PatLeaf<(i32 imm), [{
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return (uint32_t)N->getValue() < 256;
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}]>;
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def imm0_255_comp : PatLeaf<(i32 imm), [{
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return ~((uint32_t)N->getValue()) < 256;
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}]>;
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def imm8_255 : PatLeaf<(i32 imm), [{
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return (uint32_t)N->getValue() >= 8 && (uint32_t)N->getValue() < 256;
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}]>;
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def imm8_255_neg : PatLeaf<(i32 imm), [{
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unsigned Val = -N->getValue();
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return Val >= 8 && Val < 256;
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}], imm_neg_XFORM>;
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// Break imm's up into two pieces: an immediate + a left shift.
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// This uses thumb_immshifted to match and thumb_immshifted_val and
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// thumb_immshifted_shamt to get the val/shift pieces.
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def thumb_immshifted : PatLeaf<(imm), [{
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return ARM_AM::isThumbImmShiftedVal((unsigned)N->getValue());
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}]>;
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def thumb_immshifted_val : SDNodeXForm<imm, [{
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unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getValue());
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return CurDAG->getTargetConstant(V, MVT::i32);
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}]>;
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def thumb_immshifted_shamt : SDNodeXForm<imm, [{
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unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getValue());
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return CurDAG->getTargetConstant(V, MVT::i32);
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}]>;
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// Define Thumb specific addressing modes.
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// t_addrmode_rr := reg + reg
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//
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def t_addrmode_rr : Operand<i32>,
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ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
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let PrintMethod = "printThumbAddrModeRROperand";
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let MIOperandInfo = (ops GPR:$base, GPR:$offsreg);
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}
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// t_addrmode_s4 := reg + reg
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// reg + imm5 * 4
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//
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def t_addrmode_s4 : Operand<i32>,
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ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
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let PrintMethod = "printThumbAddrModeS4Operand";
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
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}
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// t_addrmode_s2 := reg + reg
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// reg + imm5 * 2
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//
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def t_addrmode_s2 : Operand<i32>,
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ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
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let PrintMethod = "printThumbAddrModeS2Operand";
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
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}
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// t_addrmode_s1 := reg + reg
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// reg + imm5
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//
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def t_addrmode_s1 : Operand<i32>,
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ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
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let PrintMethod = "printThumbAddrModeS1Operand";
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
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}
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// t_addrmode_sp := sp + imm8 * 4
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//
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def t_addrmode_sp : Operand<i32>,
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ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
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let PrintMethod = "printThumbAddrModeSPOperand";
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
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}
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//===----------------------------------------------------------------------===//
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// Miscellaneous Instructions.
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//
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let Defs = [SP], Uses = [SP] in {
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def tADJCALLSTACKUP :
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PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2),
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"@ tADJCALLSTACKUP $amt1",
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[(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb]>;
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def tADJCALLSTACKDOWN :
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PseudoInst<(outs), (ins i32imm:$amt),
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"@ tADJCALLSTACKDOWN $amt",
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[(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb]>;
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}
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let isNotDuplicable = 1 in
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def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp),
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"$cp:\n\tadd $dst, pc",
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[(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
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//===----------------------------------------------------------------------===//
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// Control Flow Instructions.
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//
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let isReturn = 1, isTerminator = 1 in {
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def tBX_RET : TI<(outs), (ins), "bx lr", [(ARMretflag)]>;
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// Alternative return instruction used by vararg functions.
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def tBX_RET_vararg : TI<(outs), (ins GPR:$target), "bx $target", []>;
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}
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// FIXME: remove when we have a way to marking a MI with these properties.
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let isReturn = 1, isTerminator = 1 in
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def tPOP_RET : TI<(outs reglist:$dst1, variable_ops), (ins),
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"pop $dst1", []>;
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let isCall = 1,
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Defs = [R0, R1, R2, R3, LR,
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D0, D1, D2, D3, D4, D5, D6, D7] in {
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def tBL : TIx2<(outs), (ins i32imm:$func, variable_ops),
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"bl ${func:call}",
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[(ARMtcall tglobaladdr:$func)]>;
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// ARMv5T and above
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def tBLXi : TIx2<(outs), (ins i32imm:$func, variable_ops),
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"blx ${func:call}",
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[(ARMcall tglobaladdr:$func)]>, Requires<[HasV5T]>;
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def tBLXr : TI<(outs), (ins GPR:$func, variable_ops),
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"blx $func",
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[(ARMtcall GPR:$func)]>, Requires<[HasV5T]>;
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// ARMv4T
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def tBX : TIx2<(outs), (ins GPR:$func, variable_ops),
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"cpy lr, pc\n\tbx $func",
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[(ARMcall_nolink GPR:$func)]>;
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}
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let isBranch = 1, isTerminator = 1 in {
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let isBarrier = 1 in {
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let isPredicable = 1 in
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def tB : TI<(outs), (ins brtarget:$target), "b $target",
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[(br bb:$target)]>;
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// Far jump
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def tBfar : TIx2<(outs), (ins brtarget:$target), "bl $target\t@ far jump",[]>;
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def tBR_JTr : TJTI<(outs),
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(ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
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"cpy pc, $target \n\t.align\t2\n$jt",
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[(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
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}
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}
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// FIXME: should be able to write a pattern for ARMBrcond, but can't use
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// a two-value operand where a dag node expects two operands. :(
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let isBranch = 1, isTerminator = 1 in
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def tBcc : TI<(outs), (ins brtarget:$target, pred:$cc), "b$cc $target",
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[/*(ARMbrcond bb:$target, imm:$cc)*/]>;
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//===----------------------------------------------------------------------===//
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// Load Store Instructions.
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//
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let isSimpleLoad = 1 in
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def tLDR : TI4<(outs GPR:$dst), (ins t_addrmode_s4:$addr),
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"ldr $dst, $addr",
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[(set GPR:$dst, (load t_addrmode_s4:$addr))]>;
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def tLDRB : TI1<(outs GPR:$dst), (ins t_addrmode_s1:$addr),
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"ldrb $dst, $addr",
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[(set GPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
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def tLDRH : TI2<(outs GPR:$dst), (ins t_addrmode_s2:$addr),
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"ldrh $dst, $addr",
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[(set GPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
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def tLDRSB : TI1<(outs GPR:$dst), (ins t_addrmode_rr:$addr),
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"ldrsb $dst, $addr",
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[(set GPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
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def tLDRSH : TI2<(outs GPR:$dst), (ins t_addrmode_rr:$addr),
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"ldrsh $dst, $addr",
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[(set GPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
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let isSimpleLoad = 1 in
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def tLDRspi : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr),
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"ldr $dst, $addr",
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[(set GPR:$dst, (load t_addrmode_sp:$addr))]>;
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// Special instruction for restore. It cannot clobber condition register
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// when it's expanded by eliminateCallFramePseudoInstr().
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let isSimpleLoad = 1, mayLoad = 1 in
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def tRestore : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr),
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"ldr $dst, $addr", []>;
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// Load tconstpool
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let isSimpleLoad = 1 in
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def tLDRpci : TIs<(outs GPR:$dst), (ins i32imm:$addr),
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"ldr $dst, $addr",
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[(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
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// Special LDR for loads from non-pc-relative constpools.
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let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1 in
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def tLDRcp : TIs<(outs GPR:$dst), (ins i32imm:$addr),
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"ldr $dst, $addr", []>;
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def tSTR : TI4<(outs), (ins GPR:$src, t_addrmode_s4:$addr),
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"str $src, $addr",
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[(store GPR:$src, t_addrmode_s4:$addr)]>;
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def tSTRB : TI1<(outs), (ins GPR:$src, t_addrmode_s1:$addr),
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"strb $src, $addr",
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[(truncstorei8 GPR:$src, t_addrmode_s1:$addr)]>;
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def tSTRH : TI2<(outs), (ins GPR:$src, t_addrmode_s2:$addr),
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"strh $src, $addr",
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[(truncstorei16 GPR:$src, t_addrmode_s2:$addr)]>;
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def tSTRspi : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr),
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"str $src, $addr",
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[(store GPR:$src, t_addrmode_sp:$addr)]>;
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let mayStore = 1 in {
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// Special instruction for spill. It cannot clobber condition register
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// when it's expanded by eliminateCallFramePseudoInstr().
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def tSpill : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr),
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"str $src, $addr", []>;
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}
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//===----------------------------------------------------------------------===//
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// Load / store multiple Instructions.
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//
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// TODO: A7-44: LDMIA - load multiple
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let mayLoad = 1 in
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def tPOP : TI<(outs reglist:$dst1, variable_ops), (ins),
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"pop $dst1", []>;
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let mayStore = 1 in
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def tPUSH : TI<(outs), (ins reglist:$src1, variable_ops),
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"push $src1", []>;
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//===----------------------------------------------------------------------===//
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// Arithmetic Instructions.
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//
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// Add with carry
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def tADC : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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"adc $dst, $rhs",
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[(set GPR:$dst, (adde GPR:$lhs, GPR:$rhs))]>;
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def tADDS : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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"add $dst, $lhs, $rhs",
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[(set GPR:$dst, (addc GPR:$lhs, GPR:$rhs))]>;
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def tADDi3 : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
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"add $dst, $lhs, $rhs",
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[(set GPR:$dst, (add GPR:$lhs, imm0_7:$rhs))]>;
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def tADDi8 : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
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"add $dst, $rhs",
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[(set GPR:$dst, (add GPR:$lhs, imm8_255:$rhs))]>;
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def tADDrr : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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"add $dst, $lhs, $rhs",
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[(set GPR:$dst, (add GPR:$lhs, GPR:$rhs))]>;
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def tADDhirr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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"add $dst, $rhs", []>;
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def tADDrPCi : TI<(outs GPR:$dst), (ins i32imm:$rhs),
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"add $dst, pc, $rhs * 4", []>;
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def tADDrSPi : TI<(outs GPR:$dst), (ins GPR:$sp, i32imm:$rhs),
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"add $dst, $sp, $rhs * 4", []>;
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def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
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"add $dst, $rhs * 4", []>;
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def tAND : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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"and $dst, $rhs",
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[(set GPR:$dst, (and GPR:$lhs, GPR:$rhs))]>;
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def tASRri : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
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"asr $dst, $lhs, $rhs",
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[(set GPR:$dst, (sra GPR:$lhs, imm:$rhs))]>;
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def tASRrr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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"asr $dst, $rhs",
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[(set GPR:$dst, (sra GPR:$lhs, GPR:$rhs))]>;
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def tBIC : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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"bic $dst, $rhs",
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[(set GPR:$dst, (and GPR:$lhs, (not GPR:$rhs)))]>;
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def tCMN : TI<(outs), (ins GPR:$lhs, GPR:$rhs),
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"cmn $lhs, $rhs",
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[(ARMcmp GPR:$lhs, (ineg GPR:$rhs))]>;
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def tCMPi8 : TI<(outs), (ins GPR:$lhs, i32imm:$rhs),
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"cmp $lhs, $rhs",
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[(ARMcmp GPR:$lhs, imm0_255:$rhs)]>;
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def tCMPr : TI<(outs), (ins GPR:$lhs, GPR:$rhs),
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"cmp $lhs, $rhs",
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[(ARMcmp GPR:$lhs, GPR:$rhs)]>;
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def tTST : TI<(outs), (ins GPR:$lhs, GPR:$rhs),
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"tst $lhs, $rhs",
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[(ARMcmpNZ (and GPR:$lhs, GPR:$rhs), 0)]>;
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def tCMNNZ : TI<(outs), (ins GPR:$lhs, GPR:$rhs),
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"cmn $lhs, $rhs",
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[(ARMcmpNZ GPR:$lhs, (ineg GPR:$rhs))]>;
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def tCMPNZi8 : TI<(outs), (ins GPR:$lhs, i32imm:$rhs),
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"cmp $lhs, $rhs",
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[(ARMcmpNZ GPR:$lhs, imm0_255:$rhs)]>;
|
|
|
|
def tCMPNZr : TI<(outs), (ins GPR:$lhs, GPR:$rhs),
|
|
"cmp $lhs, $rhs",
|
|
[(ARMcmpNZ GPR:$lhs, GPR:$rhs)]>;
|
|
|
|
// TODO: A7-37: CMP(3) - cmp hi regs
|
|
|
|
def tEOR : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
|
|
"eor $dst, $rhs",
|
|
[(set GPR:$dst, (xor GPR:$lhs, GPR:$rhs))]>;
|
|
|
|
def tLSLri : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
|
|
"lsl $dst, $lhs, $rhs",
|
|
[(set GPR:$dst, (shl GPR:$lhs, imm:$rhs))]>;
|
|
|
|
def tLSLrr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
|
|
"lsl $dst, $rhs",
|
|
[(set GPR:$dst, (shl GPR:$lhs, GPR:$rhs))]>;
|
|
|
|
def tLSRri : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
|
|
"lsr $dst, $lhs, $rhs",
|
|
[(set GPR:$dst, (srl GPR:$lhs, imm:$rhs))]>;
|
|
|
|
def tLSRrr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
|
|
"lsr $dst, $rhs",
|
|
[(set GPR:$dst, (srl GPR:$lhs, GPR:$rhs))]>;
|
|
|
|
// FIXME: This is not rematerializable because mov changes the condition code.
|
|
def tMOVi8 : TI<(outs GPR:$dst), (ins i32imm:$src),
|
|
"mov $dst, $src",
|
|
[(set GPR:$dst, imm0_255:$src)]>;
|
|
|
|
// TODO: A7-73: MOV(2) - mov setting flag.
|
|
|
|
|
|
// Note: MOV(2) of two low regs updates the flags, so we emit this as 'cpy',
|
|
// which is MOV(3). This also supports high registers.
|
|
def tMOVr : TI<(outs GPR:$dst), (ins GPR:$src),
|
|
"cpy $dst, $src", []>;
|
|
|
|
def tMUL : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
|
|
"mul $dst, $rhs",
|
|
[(set GPR:$dst, (mul GPR:$lhs, GPR:$rhs))]>;
|
|
|
|
def tMVN : TI<(outs GPR:$dst), (ins GPR:$src),
|
|
"mvn $dst, $src",
|
|
[(set GPR:$dst, (not GPR:$src))]>;
|
|
|
|
def tNEG : TI<(outs GPR:$dst), (ins GPR:$src),
|
|
"neg $dst, $src",
|
|
[(set GPR:$dst, (ineg GPR:$src))]>;
|
|
|
|
def tORR : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
|
|
"orr $dst, $rhs",
|
|
[(set GPR:$dst, (or GPR:$lhs, GPR:$rhs))]>;
|
|
|
|
|
|
def tREV : TI<(outs GPR:$dst), (ins GPR:$src),
|
|
"rev $dst, $src",
|
|
[(set GPR:$dst, (bswap GPR:$src))]>,
|
|
Requires<[IsThumb, HasV6]>;
|
|
|
|
def tREV16 : TI<(outs GPR:$dst), (ins GPR:$src),
|
|
"rev16 $dst, $src",
|
|
[(set GPR:$dst,
|
|
(or (and (srl GPR:$src, 8), 0xFF),
|
|
(or (and (shl GPR:$src, 8), 0xFF00),
|
|
(or (and (srl GPR:$src, 8), 0xFF0000),
|
|
(and (shl GPR:$src, 8), 0xFF000000)))))]>,
|
|
Requires<[IsThumb, HasV6]>;
|
|
|
|
def tREVSH : TI<(outs GPR:$dst), (ins GPR:$src),
|
|
"revsh $dst, $src",
|
|
[(set GPR:$dst,
|
|
(sext_inreg
|
|
(or (srl (and GPR:$src, 0xFFFF), 8),
|
|
(shl GPR:$src, 8)), i16))]>,
|
|
Requires<[IsThumb, HasV6]>;
|
|
|
|
def tROR : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
|
|
"ror $dst, $rhs",
|
|
[(set GPR:$dst, (rotr GPR:$lhs, GPR:$rhs))]>;
|
|
|
|
|
|
// Subtract with carry
|
|
def tSBC : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
|
|
"sbc $dst, $rhs",
|
|
[(set GPR:$dst, (sube GPR:$lhs, GPR:$rhs))]>;
|
|
|
|
def tSUBS : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
|
|
"sub $dst, $lhs, $rhs",
|
|
[(set GPR:$dst, (subc GPR:$lhs, GPR:$rhs))]>;
|
|
|
|
|
|
// TODO: A7-96: STMIA - store multiple.
|
|
|
|
def tSUBi3 : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
|
|
"sub $dst, $lhs, $rhs",
|
|
[(set GPR:$dst, (add GPR:$lhs, imm0_7_neg:$rhs))]>;
|
|
|
|
def tSUBi8 : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
|
|
"sub $dst, $rhs",
|
|
[(set GPR:$dst, (add GPR:$lhs, imm8_255_neg:$rhs))]>;
|
|
|
|
def tSUBrr : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
|
|
"sub $dst, $lhs, $rhs",
|
|
[(set GPR:$dst, (sub GPR:$lhs, GPR:$rhs))]>;
|
|
|
|
def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
|
|
"sub $dst, $rhs * 4", []>;
|
|
|
|
def tSXTB : TI<(outs GPR:$dst), (ins GPR:$src),
|
|
"sxtb $dst, $src",
|
|
[(set GPR:$dst, (sext_inreg GPR:$src, i8))]>,
|
|
Requires<[IsThumb, HasV6]>;
|
|
def tSXTH : TI<(outs GPR:$dst), (ins GPR:$src),
|
|
"sxth $dst, $src",
|
|
[(set GPR:$dst, (sext_inreg GPR:$src, i16))]>,
|
|
Requires<[IsThumb, HasV6]>;
|
|
|
|
|
|
def tUXTB : TI<(outs GPR:$dst), (ins GPR:$src),
|
|
"uxtb $dst, $src",
|
|
[(set GPR:$dst, (and GPR:$src, 0xFF))]>,
|
|
Requires<[IsThumb, HasV6]>;
|
|
def tUXTH : TI<(outs GPR:$dst), (ins GPR:$src),
|
|
"uxth $dst, $src",
|
|
[(set GPR:$dst, (and GPR:$src, 0xFFFF))]>,
|
|
Requires<[IsThumb, HasV6]>;
|
|
|
|
|
|
// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
|
|
// Expanded by the scheduler into a branch sequence.
|
|
let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
|
|
def tMOVCCr :
|
|
PseudoInst<(outs GPR:$dst), (ins GPR:$false, GPR:$true, pred:$cc),
|
|
"@ tMOVCCr $cc",
|
|
[/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))*/]>;
|
|
|
|
// tLEApcrel - Load a pc-relative address into a register without offending the
|
|
// assembler.
|
|
def tLEApcrel : TIx2<(outs GPR:$dst), (ins i32imm:$label),
|
|
!strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
|
|
"${:private}PCRELL${:uid}+4))\n"),
|
|
!strconcat("\tmov $dst, #PCRELV${:uid}\n",
|
|
"${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
|
|
[]>;
|
|
|
|
def tLEApcrelJT : TIx2<(outs GPR:$dst), (ins i32imm:$label, i32imm:$id),
|
|
!strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
|
|
"${:private}PCRELL${:uid}+4))\n"),
|
|
!strconcat("\tmov $dst, #PCRELV${:uid}\n",
|
|
"${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
|
|
[]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// TLS Instructions
|
|
//
|
|
|
|
// __aeabi_read_tp preserves the registers r1-r3.
|
|
let isCall = 1,
|
|
Defs = [R0, LR] in {
|
|
def tTPsoft : TIx2<(outs), (ins),
|
|
"bl __aeabi_read_tp",
|
|
[(set R0, ARMthread_pointer)]>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Non-Instruction Patterns
|
|
//
|
|
|
|
// ConstantPool, GlobalAddress
|
|
def : ThumbPat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
|
|
def : ThumbPat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
|
|
|
|
// JumpTable
|
|
def : ThumbPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
|
|
(tLEApcrelJT tjumptable:$dst, imm:$id)>;
|
|
|
|
// Direct calls
|
|
def : ThumbPat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>;
|
|
def : ThumbV5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>;
|
|
|
|
// Indirect calls to ARM routines
|
|
def : ThumbV5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>;
|
|
|
|
// zextload i1 -> zextload i8
|
|
def : ThumbPat<(zextloadi1 t_addrmode_s1:$addr),
|
|
(tLDRB t_addrmode_s1:$addr)>;
|
|
|
|
// extload -> zextload
|
|
def : ThumbPat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
|
|
def : ThumbPat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
|
|
def : ThumbPat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
|
|
|
|
// Large immediate handling.
|
|
|
|
// Two piece imms.
|
|
def : ThumbPat<(i32 thumb_immshifted:$src),
|
|
(tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
|
|
(thumb_immshifted_shamt imm:$src))>;
|
|
|
|
def : ThumbPat<(i32 imm0_255_comp:$src),
|
|
(tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
|