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https://github.com/c64scene-ar/llvm-6502.git
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b5a55d979c
non-zero. - Teach X86 cmov optimization to eliminate the cmov from ctlz, cttz extension when the source of X86ISD::BSR / X86ISD::BSF is proven to be non-zero. rdar://9490949 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131948 91177308-0d34-0410-b5e6-96231b3b80d8
49 lines
997 B
LLVM
49 lines
997 B
LLVM
; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s
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define i32 @t1(i32 %x) nounwind {
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%tmp = tail call i32 @llvm.ctlz.i32( i32 %x )
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ret i32 %tmp
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; CHECK: t1:
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; CHECK: bsrl
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; CHECK: cmov
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}
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declare i32 @llvm.ctlz.i32(i32) nounwind readnone
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define i32 @t2(i32 %x) nounwind {
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%tmp = tail call i32 @llvm.cttz.i32( i32 %x )
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ret i32 %tmp
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; CHECK: t2:
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; CHECK: bsfl
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; CHECK: cmov
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}
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declare i32 @llvm.cttz.i32(i32) nounwind readnone
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define i16 @t3(i16 %x, i16 %y) nounwind {
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entry:
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%tmp1 = add i16 %x, %y
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%tmp2 = tail call i16 @llvm.ctlz.i16( i16 %tmp1 ) ; <i16> [#uses=1]
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ret i16 %tmp2
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; CHECK: t3:
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; CHECK: bsrw
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; CHECK: cmov
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}
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declare i16 @llvm.ctlz.i16(i16) nounwind readnone
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; Don't generate the cmovne when the source is known non-zero (and bsr would
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; not set ZF).
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; rdar://9490949
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define i32 @t4(i32 %n) nounwind {
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entry:
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; CHECK: t4:
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; CHECK: bsrl
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; CHECK-NOT: cmov
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; CHECK: ret
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%or = or i32 %n, 1
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%tmp1 = tail call i32 @llvm.ctlz.i32(i32 %or)
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ret i32 %tmp1
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}
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