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https://github.com/c64scene-ar/llvm-6502.git
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2dbe929685
The stack realignment code was fixed to work when there is stack realignment and a dynamic alloca is present so this shouldn't cause correctness issues anymore. Note that this also enables generation of AVX instructions for memset under the assumptions: - Unaligned loads/stores are always fast on CPUs supporting AVX - AVX is not slower than SSE We may need some tweaked heuristics if one of those assumptions turns out not to be true. Effectively reverts r58317. Part of PR2962. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167967 91177308-0d34-0410-b5e6-96231b3b80d8
78 lines
1.8 KiB
LLVM
78 lines
1.8 KiB
LLVM
; Make sure that we realign the stack. Mingw32 uses 4 byte stack alignment, we
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; need 16 bytes for SSE and 32 bytes for AVX.
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; RUN: llc < %s -mtriple=i386-pc-mingw32 -mcpu=pentium2 | FileCheck %s -check-prefix=NOSSE
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; RUN: llc < %s -mtriple=i386-pc-mingw32 -mcpu=pentium3 | FileCheck %s -check-prefix=SSE1
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; RUN: llc < %s -mtriple=i386-pc-mingw32 -mcpu=yonah | FileCheck %s -check-prefix=SSE2
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; RUN: llc < %s -mtriple=i386-pc-mingw32 -mcpu=corei7-avx | FileCheck %s -check-prefix=AVX1
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; RUN: llc < %s -mtriple=i386-pc-mingw32 -mcpu=core-avx2 | FileCheck %s -check-prefix=AVX2
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define void @test1(i32 %t) nounwind {
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%tmp1210 = alloca i8, i32 32, align 4
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call void @llvm.memset.p0i8.i64(i8* %tmp1210, i8 0, i64 32, i32 4, i1 false)
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%x = alloca i8, i32 %t
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call void @dummy(i8* %x)
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ret void
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; NOSSE: test1:
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; NOSSE-NOT: and
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; NOSSE: movl $0
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; SSE1: test1:
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; SSE1: andl $-16
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; SSE1: movl %esp, %esi
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; SSE1: movaps
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; SSE2: test1:
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; SSE2: andl $-16
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; SSE2: movl %esp, %esi
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; SSE2: movaps
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; AVX1: test1:
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; AVX1: andl $-32
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; AVX1: movl %esp, %esi
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; AVX1: vmovaps %ymm
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; AVX2: test1:
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; AVX2: andl $-32
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; AVX2: movl %esp, %esi
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; AVX2: vmovaps %ymm
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}
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define void @test2(i32 %t) nounwind {
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%tmp1210 = alloca i8, i32 16, align 4
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call void @llvm.memset.p0i8.i64(i8* %tmp1210, i8 0, i64 16, i32 4, i1 false)
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%x = alloca i8, i32 %t
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call void @dummy(i8* %x)
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ret void
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; NOSSE: test2:
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; NOSSE-NOT: and
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; NOSSE: movl $0
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; SSE1: test2:
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; SSE1: andl $-16
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; SSE1: movl %esp, %esi
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; SSE1: movaps
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; SSE2: test2:
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; SSE2: andl $-16
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; SSE2: movl %esp, %esi
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; SSE2: movaps
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; AVX1: test2:
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; AVX1: andl $-16
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; AVX1: movl %esp, %esi
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; AVX1: vmovaps %xmm
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; AVX2: test2:
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; AVX2: andl $-16
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; AVX2: movl %esp, %esi
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; AVX2: vmovaps %xmm
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}
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declare void @dummy(i8*)
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declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
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