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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70695 91177308-0d34-0410-b5e6-96231b3b80d8
58 lines
1.8 KiB
TableGen
58 lines
1.8 KiB
TableGen
//===- MSP430RegisterInfo.td - MSP430 Register defs ----------*- tblgen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the MSP430 register file
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//===----------------------------------------------------------------------===//
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class MSP430Reg<bits<4> num, string n> : Register<n> {
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field bits<4> Num = num;
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let Namespace = "MSP430";
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}
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//===----------------------------------------------------------------------===//
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// Registers
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//===----------------------------------------------------------------------===//
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def PC : MSP430Reg<0, "PC">;
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def SP : MSP430Reg<1, "SP">;
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def SR : MSP430Reg<2, "SR">;
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def CG : MSP430Reg<3, "CG">;
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def R4 : MSP430Reg<4, "R4">;
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def R5 : MSP430Reg<5, "R5">;
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def R6 : MSP430Reg<6, "R6">;
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def R7 : MSP430Reg<7, "R7">;
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def R8 : MSP430Reg<8, "R8">;
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def R9 : MSP430Reg<9, "R9">;
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def R10 : MSP430Reg<10, "R10">;
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def R11 : MSP430Reg<11, "R11">;
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def R12 : MSP430Reg<12, "R12">;
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def R13 : MSP430Reg<13, "R13">;
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def R14 : MSP430Reg<14, "R14">;
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def R15 : MSP430Reg<15, "R15">;
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def MSP430Regs : RegisterClass<"MSP430", [i16], 16,
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// Volatile registers
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[R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15,
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// Volatile, but not allocable
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PC, SP, SR, CG]>
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{
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let MethodProtos = [{
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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MSP430RegsClass::iterator
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MSP430RegsClass::allocation_order_end(const MachineFunction &MF) const {
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// The last 4 registers on the list above are reserved
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return end()-4;
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}
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}];
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}
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