mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
561c44fc33
One code change and several test changes to match that details in http://reviews.llvm.org/D9481 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237150 91177308-0d34-0410-b5e6-96231b3b80d8
143 lines
5.6 KiB
LLVM
143 lines
5.6 KiB
LLVM
; REQUIRES: asserts
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; RUN: opt -loop-unswitch -loop-unswitch-threshold 1000 -disable-output -stats -info-output-file - < %s | FileCheck --check-prefix=STATS %s
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; RUN: opt -S -loop-unswitch -loop-unswitch-threshold 1000 -verify-loop-info -verify-dom-info < %s | FileCheck %s
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; STATS: 1 loop-simplify - Number of pre-header or exit blocks inserted
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; STATS: 3 loop-unswitch - Number of switches unswitched
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; CHECK: %1 = icmp eq i32 %c, 1
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; CHECK-NEXT: br i1 %1, label %.split.us, label %..split_crit_edge
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; CHECK: ..split_crit_edge: ; preds = %0
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; CHECK-NEXT: br label %.split
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; CHECK: .split.us: ; preds = %0
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; CHECK-NEXT: %2 = icmp eq i32 %d, 1
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; CHECK-NEXT: br i1 %2, label %.split.us.split.us, label %.split.us..split.us.split_crit_edge
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; CHECK: .split.us..split.us.split_crit_edge: ; preds = %.split.us
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; CHECK-NEXT: br label %.split.us.split
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; CHECK: .split.us.split.us: ; preds = %.split.us
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; CHECK-NEXT: br label %loop_begin.us.us
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; CHECK: loop_begin.us.us: ; preds = %loop_begin.backedge.us.us, %.split.us.split.us
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; CHECK-NEXT: %var_val.us.us = load i32, i32* %var
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; CHECK-NEXT: switch i32 1, label %second_switch.us.us [
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; CHECK-NEXT: i32 1, label %inc.us.us
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; CHECK: second_switch.us.us: ; preds = %loop_begin.us.us
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; CHECK-NEXT: switch i32 1, label %default.us.us [
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; CHECK-NEXT: i32 1, label %inc.us.us
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; CHECK: inc.us.us: ; preds = %second_switch.us.us, %loop_begin.us.us
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; CHECK-NEXT: call void @incf() [[NOR_NUW:#[0-9]+]]
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; CHECK-NEXT: br label %loop_begin.backedge.us.us
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; CHECK: .split.us.split: ; preds = %.split.us..split.us.split_crit_edge
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; CHECK-NEXT: br label %loop_begin.us
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; CHECK: loop_begin.us: ; preds = %loop_begin.backedge.us, %.split.us.split
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; CHECK-NEXT: %var_val.us = load i32, i32* %var
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; CHECK-NEXT: switch i32 1, label %second_switch.us [
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; CHECK-NEXT: i32 1, label %inc.us
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; CHECK: second_switch.us: ; preds = %loop_begin.us
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; CHECK-NEXT: switch i32 %d, label %default.us [
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; CHECK-NEXT: i32 1, label %second_switch.us.inc.us_crit_edge
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; CHECK-NEXT: ]
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; CHECK: second_switch.us.inc.us_crit_edge: ; preds = %second_switch.us
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; CHECK-NEXT: br i1 true, label %us-unreachable8, label %inc.us
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; CHECK: inc.us: ; preds = %second_switch.us.inc.us_crit_edge, %loop_begin.us
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; CHECK-NEXT: call void @incf() [[NOR_NUW]]
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; CHECK-NEXT: br label %loop_begin.backedge.us
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; CHECK: .split: ; preds = %..split_crit_edge
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; CHECK-NEXT: %3 = icmp eq i32 %d, 1
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; CHECK-NEXT: br i1 %3, label %.split.split.us, label %.split..split.split_crit_edge
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; CHECK: .split..split.split_crit_edge: ; preds = %.split
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; CHECK-NEXT: br label %.split.split
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; CHECK: .split.split.us: ; preds = %.split
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; CHECK-NEXT: br label %loop_begin.us1
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; CHECK: loop_begin.us1: ; preds = %loop_begin.backedge.us6, %.split.split.us
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; CHECK-NEXT: %var_val.us.2 = load i32, i32* %var
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; CHECK-NEXT: switch i32 %c, label %second_switch.us3 [
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; CHECK-NEXT: i32 1, label %loop_begin.inc_crit_edge.us
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; CHECK-NEXT: ]
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; CHECK: second_switch.us3: ; preds = %loop_begin.us1
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; CHECK-NEXT: switch i32 1, label %default.us5 [
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; CHECK-NEXT: i32 1, label %inc.us4
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; CHECK-NEXT: ]
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; CHECK: inc.us4: ; preds = %loop_begin.inc_crit_edge.us, %second_switch.us3
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; CHECK-NEXT: call void @incf() [[NOR_NUW]]
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; CHECK-NEXT: br label %loop_begin.backedge.us6
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; CHECK: loop_begin.inc_crit_edge.us: ; preds = %loop_begin.us1
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; CHECK-NEXT: br i1 true, label %us-unreachable.us-lcssa.us, label %inc.us4
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; CHECK: .split.split: ; preds = %.split..split.split_crit_edge
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; CHECK-NEXT: br label %loop_begin
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; CHECK: loop_begin: ; preds = %loop_begin.backedge, %.split.split
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; CHECK-NEXT: %var_val = load i32, i32* %var
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; CHECK-NEXT: switch i32 %c, label %second_switch [
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; CHECK-NEXT: i32 1, label %loop_begin.inc_crit_edge
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; CHECK-NEXT: ]
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; CHECK: loop_begin.inc_crit_edge: ; preds = %loop_begin
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; CHECK-NEXT: br i1 true, label %us-unreachable.us-lcssa, label %inc
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; CHECK: second_switch: ; preds = %loop_begin
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; CHECK-NEXT: switch i32 %d, label %default [
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; CHECK-NEXT: i32 1, label %second_switch.inc_crit_edge
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; CHECK-NEXT: ]
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; CHECK: second_switch.inc_crit_edge: ; preds = %second_switch
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; CHECK-NEXT: br i1 true, label %us-unreachable7, label %inc
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define i32 @test(i32* %var) {
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%mem = alloca i32
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store i32 2, i32* %mem
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%c = load i32, i32* %mem
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%d = load i32, i32* %mem
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br label %loop_begin
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loop_begin:
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%var_val = load i32, i32* %var
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switch i32 %c, label %second_switch [
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i32 1, label %inc
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]
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second_switch:
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switch i32 %d, label %default [
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i32 1, label %inc
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]
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inc:
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call void @incf() noreturn nounwind
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br label %loop_begin
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default:
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br label %loop_begin
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loop_exit:
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ret i32 0
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}
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declare void @incf() noreturn
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declare void @decf() noreturn
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; CHECK: attributes #0 = { noreturn }
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; CHECK: attributes [[NOR_NUW]] = { noreturn nounwind }
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