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99cf50937d
that are smaller than an int, make sure to adjust the frame pointer to take this into consideration. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25351 91177308-0d34-0410-b5e6-96231b3b80d8
1034 lines
39 KiB
C++
1034 lines
39 KiB
C++
//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the V8 target
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//
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//===----------------------------------------------------------------------===//
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#include "SparcV8.h"
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#include "SparcV8TargetMachine.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Support/Debug.h"
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#include <iostream>
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// TargetLowering Implementation
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//===----------------------------------------------------------------------===//
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namespace V8ISD {
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enum {
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FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END,
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CMPICC, // Compare two GPR operands, set icc.
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CMPFCC, // Compare two FP operands, set fcc.
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BRICC, // Branch to dest on icc condition
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BRFCC, // Branch to dest on fcc condition
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Hi, Lo, // Hi/Lo operations, typically on a global address.
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FTOI, // FP to Int within a FP register.
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ITOF, // Int to FP within a FP register.
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SELECT_ICC, // Select between two values using the current ICC flags.
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SELECT_FCC, // Select between two values using the current FCC flags.
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RET_FLAG, // Return with a flag operand.
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};
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}
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namespace {
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class SparcV8TargetLowering : public TargetLowering {
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int VarArgsFrameOffset; // Frame offset to start of varargs area.
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public:
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SparcV8TargetLowering(TargetMachine &TM);
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virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
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virtual std::vector<SDOperand>
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LowerArguments(Function &F, SelectionDAG &DAG);
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virtual std::pair<SDOperand, SDOperand>
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LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
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unsigned CC,
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bool isTailCall, SDOperand Callee, ArgListTy &Args,
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SelectionDAG &DAG);
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virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op,
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SelectionDAG &DAG);
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virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
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Value *VAListV, SelectionDAG &DAG);
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virtual std::pair<SDOperand,SDOperand>
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LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
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const Type *ArgTy, SelectionDAG &DAG);
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virtual std::pair<SDOperand, SDOperand>
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LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
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SelectionDAG &DAG);
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virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *MBB);
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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};
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}
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SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
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: TargetLowering(TM) {
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// Set up the register classes.
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addRegisterClass(MVT::i32, V8::IntRegsRegisterClass);
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addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
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addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
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// Custom legalize GlobalAddress nodes into LO/HI parts.
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
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// Sparc doesn't have sext_inreg, replace them with shl/sra
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
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// Sparc has no REM operation.
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setOperationAction(ISD::UREM, MVT::i32, Expand);
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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// Custom expand fp<->sint
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setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
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setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
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// Expand fp<->uint
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
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setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
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setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
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setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
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// Turn FP extload into load/fextend
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setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
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// Sparc has no select or setcc: expand to SELECT_CC.
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setOperationAction(ISD::SELECT, MVT::i32, Expand);
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setOperationAction(ISD::SELECT, MVT::f32, Expand);
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setOperationAction(ISD::SELECT, MVT::f64, Expand);
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setOperationAction(ISD::SETCC, MVT::i32, Expand);
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setOperationAction(ISD::SETCC, MVT::f32, Expand);
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setOperationAction(ISD::SETCC, MVT::f64, Expand);
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// Sparc doesn't have BRCOND either, it has BR_CC.
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
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setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
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setOperationAction(ISD::BR_CC, MVT::i32, Custom);
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setOperationAction(ISD::BR_CC, MVT::f32, Custom);
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setOperationAction(ISD::BR_CC, MVT::f64, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
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// V8 has no intrinsics for these particular operations.
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setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
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setOperationAction(ISD::MEMSET, MVT::Other, Expand);
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setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::CTPOP, MVT::i32, Expand);
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setOperationAction(ISD::CTTZ , MVT::i32, Expand);
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setOperationAction(ISD::CTLZ , MVT::i32, Expand);
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setOperationAction(ISD::ROTL , MVT::i32, Expand);
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setOperationAction(ISD::ROTR , MVT::i32, Expand);
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setOperationAction(ISD::BSWAP, MVT::i32, Expand);
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
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// We don't have line number support yet.
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
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// Expand these to their default code.
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
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setStackPointerRegisterToSaveRestore(V8::O6);
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computeRegisterProperties();
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}
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const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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default: return 0;
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case V8ISD::CMPICC: return "V8ISD::CMPICC";
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case V8ISD::CMPFCC: return "V8ISD::CMPFCC";
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case V8ISD::BRICC: return "V8ISD::BRICC";
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case V8ISD::BRFCC: return "V8ISD::BRFCC";
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case V8ISD::Hi: return "V8ISD::Hi";
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case V8ISD::Lo: return "V8ISD::Lo";
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case V8ISD::FTOI: return "V8ISD::FTOI";
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case V8ISD::ITOF: return "V8ISD::ITOF";
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case V8ISD::SELECT_ICC: return "V8ISD::SELECT_ICC";
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case V8ISD::SELECT_FCC: return "V8ISD::SELECT_FCC";
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case V8ISD::RET_FLAG: return "V8ISD::RET_FLAG";
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}
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}
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/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
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/// either one or two GPRs, including FP values. TODO: we should pass FP values
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/// in FP registers for fastcc functions.
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std::vector<SDOperand>
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SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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MachineFunction &MF = DAG.getMachineFunction();
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SSARegMap *RegMap = MF.getSSARegMap();
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std::vector<SDOperand> ArgValues;
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static const unsigned ArgRegs[] = {
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V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5
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};
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const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
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unsigned ArgOffset = 68;
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SDOperand Root = DAG.getRoot();
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std::vector<SDOperand> OutChains;
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for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
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MVT::ValueType ObjectVT = getValueType(I->getType());
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switch (ObjectVT) {
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default: assert(0 && "Unhandled argument type!");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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if (I->use_empty()) { // Argument is dead.
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if (CurArgReg < ArgRegEnd) ++CurArgReg;
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ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
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} else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
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unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
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MF.addLiveIn(*CurArgReg++, VReg);
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SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
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if (ObjectVT != MVT::i32) {
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unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
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: ISD::AssertZext;
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Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
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DAG.getValueType(ObjectVT));
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Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
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}
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ArgValues.push_back(Arg);
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} else {
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
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SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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SDOperand Load;
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if (ObjectVT == MVT::i32) {
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Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
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} else {
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unsigned LoadOp =
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I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
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// Sparc is big endian, so add an offset based on the ObjectVT.
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unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8);
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FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
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DAG.getConstant(Offset, MVT::i32));
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Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
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DAG.getSrcValue(0), ObjectVT);
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Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
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}
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ArgValues.push_back(Load);
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}
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ArgOffset += 4;
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break;
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case MVT::f32:
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if (I->use_empty()) { // Argument is dead.
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if (CurArgReg < ArgRegEnd) ++CurArgReg;
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ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
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} else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
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// FP value is passed in an integer register.
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unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
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MF.addLiveIn(*CurArgReg++, VReg);
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SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
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Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
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ArgValues.push_back(Arg);
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}
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ArgOffset += 4;
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break;
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case MVT::i64:
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case MVT::f64:
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if (I->use_empty()) { // Argument is dead.
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if (CurArgReg < ArgRegEnd) ++CurArgReg;
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if (CurArgReg < ArgRegEnd) ++CurArgReg;
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ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
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} else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
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((CurArgReg-ArgRegs) & 1) == 0) {
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// If this is a double argument and the whole thing lives on the stack,
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// and the argument is aligned, load the double straight from the stack.
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// We can't do a load in cases like void foo([6ints], int,double),
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// because the double wouldn't be aligned!
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
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SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr,
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DAG.getSrcValue(0)));
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} else {
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SDOperand HiVal;
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if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
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unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
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MF.addLiveIn(*CurArgReg++, VRegHi);
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HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
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} else {
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
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SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
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}
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SDOperand LoVal;
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if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
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unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
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MF.addLiveIn(*CurArgReg++, VRegLo);
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LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
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} else {
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
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SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
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}
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// Compose the two halves together into an i64 unit.
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SDOperand WholeValue =
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DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
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// If we want a double, do a bit convert.
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if (ObjectVT == MVT::f64)
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WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
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ArgValues.push_back(WholeValue);
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}
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ArgOffset += 8;
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break;
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}
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}
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// Store remaining ArgRegs to the stack if this is a varargs function.
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if (F.getFunctionType()->isVarArg()) {
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// Remember the vararg offset for the va_start implementation.
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VarArgsFrameOffset = ArgOffset;
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for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
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unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
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MF.addLiveIn(*CurArgReg, VReg);
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SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
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SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(),
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Arg, FIPtr, DAG.getSrcValue(0)));
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ArgOffset += 4;
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}
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}
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if (!OutChains.empty())
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DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
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// Finally, inform the code generator which regs we return values in.
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switch (getValueType(F.getReturnType())) {
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default: assert(0 && "Unknown type!");
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case MVT::isVoid: break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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MF.addLiveOut(V8::I0);
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break;
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case MVT::i64:
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MF.addLiveOut(V8::I0);
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MF.addLiveOut(V8::I1);
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break;
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case MVT::f32:
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MF.addLiveOut(V8::F0);
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break;
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case MVT::f64:
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MF.addLiveOut(V8::D0);
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break;
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}
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return ArgValues;
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}
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std::pair<SDOperand, SDOperand>
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SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
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bool isVarArg, unsigned CC,
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bool isTailCall, SDOperand Callee,
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ArgListTy &Args, SelectionDAG &DAG) {
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MachineFunction &MF = DAG.getMachineFunction();
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// Count the size of the outgoing arguments.
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unsigned ArgsSize = 0;
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for (unsigned i = 0, e = Args.size(); i != e; ++i) {
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switch (getValueType(Args[i].second)) {
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default: assert(0 && "Unknown value type!");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::f32:
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ArgsSize += 4;
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break;
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case MVT::i64:
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case MVT::f64:
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ArgsSize += 8;
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break;
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}
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}
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if (ArgsSize > 4*6)
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ArgsSize -= 4*6; // Space for first 6 arguments is prereserved.
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else
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ArgsSize = 0;
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// Keep stack frames 8-byte aligned.
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ArgsSize = (ArgsSize+7) & ~7;
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Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
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DAG.getConstant(ArgsSize, getPointerTy()));
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SDOperand StackPtr, NullSV;
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std::vector<SDOperand> Stores;
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std::vector<SDOperand> RegValuesToPass;
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unsigned ArgOffset = 68;
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for (unsigned i = 0, e = Args.size(); i != e; ++i) {
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SDOperand Val = Args[i].first;
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MVT::ValueType ObjectVT = Val.getValueType();
|
|
SDOperand ValToStore(0, 0);
|
|
unsigned ObjSize;
|
|
switch (ObjectVT) {
|
|
default: assert(0 && "Unhandled argument type!");
|
|
case MVT::i1:
|
|
case MVT::i8:
|
|
case MVT::i16:
|
|
// Promote the integer to 32-bits. If the input type is signed, use a
|
|
// sign extend, otherwise use a zero extend.
|
|
if (Args[i].second->isSigned())
|
|
Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val);
|
|
else
|
|
Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val);
|
|
// FALL THROUGH
|
|
case MVT::i32:
|
|
ObjSize = 4;
|
|
|
|
if (RegValuesToPass.size() >= 6) {
|
|
ValToStore = Val;
|
|
} else {
|
|
RegValuesToPass.push_back(Val);
|
|
}
|
|
break;
|
|
case MVT::f32:
|
|
ObjSize = 4;
|
|
if (RegValuesToPass.size() >= 6) {
|
|
ValToStore = Val;
|
|
} else {
|
|
// Convert this to a FP value in an int reg.
|
|
Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
|
|
RegValuesToPass.push_back(Val);
|
|
}
|
|
break;
|
|
case MVT::f64:
|
|
ObjSize = 8;
|
|
// If we can store this directly into the outgoing slot, do so. We can
|
|
// do this when all ArgRegs are used and if the outgoing slot is aligned.
|
|
// FIXME: McGill/misr fails with this.
|
|
if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
|
|
ValToStore = Val;
|
|
break;
|
|
}
|
|
|
|
// Otherwise, convert this to a FP value in int regs.
|
|
Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
|
|
// FALL THROUGH
|
|
case MVT::i64:
|
|
ObjSize = 8;
|
|
if (RegValuesToPass.size() >= 6) {
|
|
ValToStore = Val; // Whole thing is passed in memory.
|
|
break;
|
|
}
|
|
|
|
// Split the value into top and bottom part. Top part goes in a reg.
|
|
SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
|
|
DAG.getConstant(1, MVT::i32));
|
|
SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
|
|
DAG.getConstant(0, MVT::i32));
|
|
RegValuesToPass.push_back(Hi);
|
|
|
|
if (RegValuesToPass.size() >= 6) {
|
|
ValToStore = Lo;
|
|
ArgOffset += 4;
|
|
ObjSize = 4;
|
|
} else {
|
|
RegValuesToPass.push_back(Lo);
|
|
}
|
|
break;
|
|
}
|
|
|
|
if (ValToStore.Val) {
|
|
if (!StackPtr.Val) {
|
|
StackPtr = DAG.getRegister(V8::O6, MVT::i32);
|
|
NullSV = DAG.getSrcValue(NULL);
|
|
}
|
|
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
|
|
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
|
|
Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
|
|
ValToStore, PtrOff, NullSV));
|
|
}
|
|
ArgOffset += ObjSize;
|
|
}
|
|
|
|
// Emit all stores, make sure the occur before any copies into physregs.
|
|
if (!Stores.empty())
|
|
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
|
|
|
|
static const unsigned ArgRegs[] = {
|
|
V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5
|
|
};
|
|
|
|
// Build a sequence of copy-to-reg nodes chained together with token chain
|
|
// and flag operands which copy the outgoing args into O[0-5].
|
|
SDOperand InFlag;
|
|
for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
|
|
Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
}
|
|
|
|
// If the callee is a GlobalAddress node (quite common, every direct call is)
|
|
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
|
|
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
|
|
Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
|
|
|
|
std::vector<MVT::ValueType> NodeTys;
|
|
NodeTys.push_back(MVT::Other); // Returns a chain
|
|
NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
|
|
if (InFlag.Val)
|
|
Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0);
|
|
else
|
|
Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee), 0);
|
|
InFlag = Chain.getValue(1);
|
|
|
|
MVT::ValueType RetTyVT = getValueType(RetTy);
|
|
SDOperand RetVal;
|
|
if (RetTyVT != MVT::isVoid) {
|
|
switch (RetTyVT) {
|
|
default: assert(0 && "Unknown value type to return!");
|
|
case MVT::i1:
|
|
case MVT::i8:
|
|
case MVT::i16:
|
|
RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
|
|
Chain = RetVal.getValue(1);
|
|
|
|
// Add a note to keep track of whether it is sign or zero extended.
|
|
RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
|
|
MVT::i32, RetVal, DAG.getValueType(RetTyVT));
|
|
RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
|
|
break;
|
|
case MVT::i32:
|
|
RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
|
|
Chain = RetVal.getValue(1);
|
|
break;
|
|
case MVT::f32:
|
|
RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag);
|
|
Chain = RetVal.getValue(1);
|
|
break;
|
|
case MVT::f64:
|
|
RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag);
|
|
Chain = RetVal.getValue(1);
|
|
break;
|
|
case MVT::i64:
|
|
SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O1, MVT::i32, InFlag);
|
|
SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32,
|
|
Lo.getValue(2));
|
|
RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
|
|
Chain = Hi.getValue(1);
|
|
break;
|
|
}
|
|
}
|
|
|
|
Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
|
|
DAG.getConstant(ArgsSize, getPointerTy()));
|
|
|
|
return std::make_pair(RetVal, Chain);
|
|
}
|
|
|
|
SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
|
|
SelectionDAG &DAG) {
|
|
SDOperand Copy;
|
|
switch (Op.getValueType()) {
|
|
default: assert(0 && "Unknown type to return!");
|
|
case MVT::i32:
|
|
Copy = DAG.getCopyToReg(Chain, V8::I0, Op, SDOperand());
|
|
break;
|
|
case MVT::f32:
|
|
Copy = DAG.getCopyToReg(Chain, V8::F0, Op, SDOperand());
|
|
break;
|
|
case MVT::f64:
|
|
Copy = DAG.getCopyToReg(Chain, V8::D0, Op, SDOperand());
|
|
break;
|
|
case MVT::i64:
|
|
SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
|
|
DAG.getConstant(1, MVT::i32));
|
|
SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
|
|
DAG.getConstant(0, MVT::i32));
|
|
Copy = DAG.getCopyToReg(Chain, V8::I0, Hi, SDOperand());
|
|
Copy = DAG.getCopyToReg(Copy, V8::I1, Lo, Copy.getValue(1));
|
|
break;
|
|
}
|
|
return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
|
|
}
|
|
|
|
SDOperand SparcV8TargetLowering::
|
|
LowerVAStart(SDOperand Chain, SDOperand VAListP, Value *VAListV,
|
|
SelectionDAG &DAG) {
|
|
|
|
SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
|
|
DAG.getRegister(V8::I6, MVT::i32),
|
|
DAG.getConstant(VarArgsFrameOffset, MVT::i32));
|
|
return DAG.getNode(ISD::STORE, MVT::Other, Chain, Offset,
|
|
VAListP, DAG.getSrcValue(VAListV));
|
|
}
|
|
|
|
std::pair<SDOperand,SDOperand> SparcV8TargetLowering::
|
|
LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
|
|
const Type *ArgTy, SelectionDAG &DAG) {
|
|
// Load the pointer out of the valist.
|
|
SDOperand Ptr = DAG.getLoad(MVT::i32, Chain,
|
|
VAListP, DAG.getSrcValue(VAListV));
|
|
MVT::ValueType ArgVT = getValueType(ArgTy);
|
|
SDOperand Val = DAG.getLoad(ArgVT, Ptr.getValue(1),
|
|
Ptr, DAG.getSrcValue(NULL));
|
|
// Increment the pointer.
|
|
Ptr = DAG.getNode(ISD::ADD, MVT::i32, Ptr,
|
|
DAG.getConstant(MVT::getSizeInBits(ArgVT)/8, MVT::i32));
|
|
// Store it back to the valist.
|
|
Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Ptr,
|
|
VAListP, DAG.getSrcValue(VAListV));
|
|
return std::make_pair(Val, Chain);
|
|
}
|
|
|
|
std::pair<SDOperand, SDOperand> SparcV8TargetLowering::
|
|
LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
|
|
SelectionDAG &DAG) {
|
|
assert(0 && "Unimp");
|
|
abort();
|
|
}
|
|
|
|
SDOperand SparcV8TargetLowering::
|
|
LowerOperation(SDOperand Op, SelectionDAG &DAG) {
|
|
switch (Op.getOpcode()) {
|
|
default: assert(0 && "Should not custom lower this!");
|
|
case ISD::GlobalAddress: {
|
|
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
|
|
SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
|
|
SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA);
|
|
SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA);
|
|
return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
|
|
}
|
|
case ISD::ConstantPool: {
|
|
Constant *C = cast<ConstantPoolSDNode>(Op)->get();
|
|
SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32);
|
|
SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP);
|
|
SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP);
|
|
return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
|
|
}
|
|
case ISD::FP_TO_SINT:
|
|
// Convert the fp value to integer in an FP register.
|
|
assert(Op.getValueType() == MVT::i32);
|
|
Op = DAG.getNode(V8ISD::FTOI, MVT::f32, Op.getOperand(0));
|
|
return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
|
|
case ISD::SINT_TO_FP: {
|
|
assert(Op.getOperand(0).getValueType() == MVT::i32);
|
|
SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
|
|
// Convert the int value to FP in an FP register.
|
|
return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Tmp);
|
|
}
|
|
case ISD::BR_CC: {
|
|
SDOperand Chain = Op.getOperand(0);
|
|
SDOperand CC = Op.getOperand(1);
|
|
SDOperand LHS = Op.getOperand(2);
|
|
SDOperand RHS = Op.getOperand(3);
|
|
SDOperand Dest = Op.getOperand(4);
|
|
|
|
// Get the condition flag.
|
|
if (LHS.getValueType() == MVT::i32) {
|
|
std::vector<MVT::ValueType> VTs;
|
|
VTs.push_back(MVT::i32);
|
|
VTs.push_back(MVT::Flag);
|
|
std::vector<SDOperand> Ops;
|
|
Ops.push_back(LHS);
|
|
Ops.push_back(RHS);
|
|
SDOperand Cond = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
|
|
return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond);
|
|
} else {
|
|
SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
|
|
return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
|
|
}
|
|
}
|
|
case ISD::SELECT_CC: {
|
|
SDOperand LHS = Op.getOperand(0);
|
|
SDOperand RHS = Op.getOperand(1);
|
|
unsigned CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
|
|
SDOperand TrueVal = Op.getOperand(2);
|
|
SDOperand FalseVal = Op.getOperand(3);
|
|
|
|
SDOperand CompareFlag;
|
|
unsigned Opc;
|
|
if (LHS.getValueType() == MVT::i32) {
|
|
std::vector<MVT::ValueType> VTs;
|
|
VTs.push_back(LHS.getValueType()); // subcc returns a value
|
|
VTs.push_back(MVT::Flag);
|
|
std::vector<SDOperand> Ops;
|
|
Ops.push_back(LHS);
|
|
Ops.push_back(RHS);
|
|
CompareFlag = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
|
|
Opc = V8ISD::SELECT_ICC;
|
|
} else {
|
|
CompareFlag = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
|
|
Opc = V8ISD::SELECT_FCC;
|
|
}
|
|
return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
|
|
DAG.getConstant(CC, MVT::i32), CompareFlag);
|
|
}
|
|
}
|
|
}
|
|
|
|
MachineBasicBlock *
|
|
SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
|
|
MachineBasicBlock *BB) {
|
|
unsigned BROpcode;
|
|
// Figure out the conditional branch opcode to use for this select_cc.
|
|
switch (MI->getOpcode()) {
|
|
default: assert(0 && "Unknown SELECT_CC!");
|
|
case V8::SELECT_CC_Int_ICC:
|
|
case V8::SELECT_CC_FP_ICC:
|
|
case V8::SELECT_CC_DFP_ICC:
|
|
// Integer compare.
|
|
switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) {
|
|
default: assert(0 && "Unknown integer condition code!");
|
|
case ISD::SETEQ: BROpcode = V8::BE; break;
|
|
case ISD::SETNE: BROpcode = V8::BNE; break;
|
|
case ISD::SETLT: BROpcode = V8::BL; break;
|
|
case ISD::SETGT: BROpcode = V8::BG; break;
|
|
case ISD::SETLE: BROpcode = V8::BLE; break;
|
|
case ISD::SETGE: BROpcode = V8::BGE; break;
|
|
case ISD::SETULT: BROpcode = V8::BCS; break;
|
|
case ISD::SETULE: BROpcode = V8::BLEU; break;
|
|
case ISD::SETUGT: BROpcode = V8::BGU; break;
|
|
case ISD::SETUGE: BROpcode = V8::BCC; break;
|
|
}
|
|
break;
|
|
case V8::SELECT_CC_Int_FCC:
|
|
case V8::SELECT_CC_FP_FCC:
|
|
case V8::SELECT_CC_DFP_FCC:
|
|
// FP compare.
|
|
switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) {
|
|
default: assert(0 && "Unknown fp condition code!");
|
|
case ISD::SETEQ: BROpcode = V8::FBE; break;
|
|
case ISD::SETNE: BROpcode = V8::FBNE; break;
|
|
case ISD::SETLT: BROpcode = V8::FBL; break;
|
|
case ISD::SETGT: BROpcode = V8::FBG; break;
|
|
case ISD::SETLE: BROpcode = V8::FBLE; break;
|
|
case ISD::SETGE: BROpcode = V8::FBGE; break;
|
|
case ISD::SETULT: BROpcode = V8::FBUL; break;
|
|
case ISD::SETULE: BROpcode = V8::FBULE; break;
|
|
case ISD::SETUGT: BROpcode = V8::FBUG; break;
|
|
case ISD::SETUGE: BROpcode = V8::FBUGE; break;
|
|
case ISD::SETUO: BROpcode = V8::FBU; break;
|
|
case ISD::SETO: BROpcode = V8::FBO; break;
|
|
case ISD::SETONE: BROpcode = V8::FBLG; break;
|
|
case ISD::SETUEQ: BROpcode = V8::FBUE; break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
// To "insert" a SELECT_CC instruction, we actually have to insert the diamond
|
|
// control-flow pattern. The incoming instruction knows the destination vreg
|
|
// to set, the condition code register to branch on, the true/false values to
|
|
// select between, and a branch opcode to use.
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
ilist<MachineBasicBlock>::iterator It = BB;
|
|
++It;
|
|
|
|
// thisMBB:
|
|
// ...
|
|
// TrueVal = ...
|
|
// [f]bCC copy1MBB
|
|
// fallthrough --> copy0MBB
|
|
MachineBasicBlock *thisMBB = BB;
|
|
MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
|
|
MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
|
|
BuildMI(BB, BROpcode, 1).addMBB(sinkMBB);
|
|
MachineFunction *F = BB->getParent();
|
|
F->getBasicBlockList().insert(It, copy0MBB);
|
|
F->getBasicBlockList().insert(It, sinkMBB);
|
|
// Update machine-CFG edges
|
|
BB->addSuccessor(copy0MBB);
|
|
BB->addSuccessor(sinkMBB);
|
|
|
|
// copy0MBB:
|
|
// %FalseValue = ...
|
|
// # fallthrough to sinkMBB
|
|
BB = copy0MBB;
|
|
|
|
// Update machine-CFG edges
|
|
BB->addSuccessor(sinkMBB);
|
|
|
|
// sinkMBB:
|
|
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
|
|
// ...
|
|
BB = sinkMBB;
|
|
BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg())
|
|
.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
|
|
.addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
|
|
|
|
delete MI; // The pseudo instruction is gone now.
|
|
return BB;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction Selector Implementation
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine
|
|
/// instructions for SelectionDAG operations.
|
|
///
|
|
namespace {
|
|
class SparcV8DAGToDAGISel : public SelectionDAGISel {
|
|
SparcV8TargetLowering V8Lowering;
|
|
public:
|
|
SparcV8DAGToDAGISel(TargetMachine &TM)
|
|
: SelectionDAGISel(V8Lowering), V8Lowering(TM) {}
|
|
|
|
SDOperand Select(SDOperand Op);
|
|
|
|
// Complex Pattern Selectors.
|
|
bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
|
|
bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset);
|
|
|
|
/// InstructionSelectBasicBlock - This callback is invoked by
|
|
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
|
|
virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
|
|
|
|
virtual const char *getPassName() const {
|
|
return "PowerPC DAG->DAG Pattern Instruction Selection";
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|
}
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|
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|
// Include the pieces autogenerated from the target description.
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|
#include "SparcV8GenDAGISel.inc"
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|
};
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|
} // end anonymous namespace
|
|
|
|
/// InstructionSelectBasicBlock - This callback is invoked by
|
|
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
|
|
void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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|
DEBUG(BB->dump());
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|
|
|
// Select target instructions for the DAG.
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|
DAG.setRoot(Select(DAG.getRoot()));
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|
CodeGenMap.clear();
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|
DAG.RemoveDeadNodes();
|
|
|
|
// Emit machine code to BB.
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|
ScheduleAndEmitDAG(DAG);
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|
}
|
|
|
|
bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
|
|
SDOperand &Offset) {
|
|
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
|
|
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return true;
|
|
}
|
|
|
|
if (Addr.getOpcode() == ISD::ADD) {
|
|
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
|
|
if (Predicate_simm13(CN)) {
|
|
if (FrameIndexSDNode *FIN =
|
|
dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
|
|
// Constant offset from frame ref.
|
|
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
|
|
} else {
|
|
Base = Select(Addr.getOperand(0));
|
|
}
|
|
Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
|
|
return true;
|
|
}
|
|
}
|
|
if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) {
|
|
Base = Select(Addr.getOperand(1));
|
|
Offset = Addr.getOperand(0).getOperand(0);
|
|
return true;
|
|
}
|
|
if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) {
|
|
Base = Select(Addr.getOperand(0));
|
|
Offset = Addr.getOperand(1).getOperand(0);
|
|
return true;
|
|
}
|
|
}
|
|
Base = Select(Addr);
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return true;
|
|
}
|
|
|
|
bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
|
|
SDOperand &R2) {
|
|
if (Addr.getOpcode() == ISD::FrameIndex) return false;
|
|
if (Addr.getOpcode() == ISD::ADD) {
|
|
if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
|
|
Predicate_simm13(Addr.getOperand(1).Val))
|
|
return false; // Let the reg+imm pattern catch this!
|
|
if (Addr.getOperand(0).getOpcode() == V8ISD::Lo ||
|
|
Addr.getOperand(1).getOpcode() == V8ISD::Lo)
|
|
return false; // Let the reg+imm pattern catch this!
|
|
R1 = Select(Addr.getOperand(0));
|
|
R2 = Select(Addr.getOperand(1));
|
|
return true;
|
|
}
|
|
|
|
R1 = Select(Addr);
|
|
R2 = CurDAG->getRegister(V8::G0, MVT::i32);
|
|
return true;
|
|
}
|
|
|
|
SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
|
|
SDNode *N = Op.Val;
|
|
if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
|
|
N->getOpcode() < V8ISD::FIRST_NUMBER)
|
|
return Op; // Already selected.
|
|
// If this has already been converted, use it.
|
|
std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
|
|
if (CGMI != CodeGenMap.end()) return CGMI->second;
|
|
|
|
switch (N->getOpcode()) {
|
|
default: break;
|
|
case ISD::FrameIndex: {
|
|
int FI = cast<FrameIndexSDNode>(N)->getIndex();
|
|
if (N->hasOneUse())
|
|
return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32,
|
|
CurDAG->getTargetFrameIndex(FI, MVT::i32),
|
|
CurDAG->getTargetConstant(0, MVT::i32));
|
|
return CodeGenMap[Op] =
|
|
CurDAG->getTargetNode(V8::ADDri, MVT::i32,
|
|
CurDAG->getTargetFrameIndex(FI, MVT::i32),
|
|
CurDAG->getTargetConstant(0, MVT::i32));
|
|
}
|
|
case ISD::ADD_PARTS: {
|
|
SDOperand LHSL = Select(N->getOperand(0));
|
|
SDOperand LHSH = Select(N->getOperand(1));
|
|
SDOperand RHSL = Select(N->getOperand(2));
|
|
SDOperand RHSH = Select(N->getOperand(3));
|
|
// FIXME, handle immediate RHS.
|
|
SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag,
|
|
LHSL, RHSL);
|
|
SDOperand Hi = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH,
|
|
Low.getValue(1));
|
|
CodeGenMap[SDOperand(N, 0)] = Low;
|
|
CodeGenMap[SDOperand(N, 1)] = Hi;
|
|
return Op.ResNo ? Hi : Low;
|
|
}
|
|
case ISD::SUB_PARTS: {
|
|
SDOperand LHSL = Select(N->getOperand(0));
|
|
SDOperand LHSH = Select(N->getOperand(1));
|
|
SDOperand RHSL = Select(N->getOperand(2));
|
|
SDOperand RHSH = Select(N->getOperand(3));
|
|
// FIXME, handle immediate RHS.
|
|
SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag,
|
|
LHSL, RHSL);
|
|
SDOperand Hi = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH,
|
|
Low.getValue(1));
|
|
CodeGenMap[SDOperand(N, 0)] = Low;
|
|
CodeGenMap[SDOperand(N, 1)] = Hi;
|
|
return Op.ResNo ? Hi : Low;
|
|
}
|
|
case ISD::SDIV:
|
|
case ISD::UDIV: {
|
|
// FIXME: should use a custom expander to expose the SRA to the dag.
|
|
SDOperand DivLHS = Select(N->getOperand(0));
|
|
SDOperand DivRHS = Select(N->getOperand(1));
|
|
|
|
// Set the Y register to the high-part.
|
|
SDOperand TopPart;
|
|
if (N->getOpcode() == ISD::SDIV) {
|
|
TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS,
|
|
CurDAG->getTargetConstant(31, MVT::i32));
|
|
} else {
|
|
TopPart = CurDAG->getRegister(V8::G0, MVT::i32);
|
|
}
|
|
TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart,
|
|
CurDAG->getRegister(V8::G0, MVT::i32));
|
|
|
|
// FIXME: Handle div by immediate.
|
|
unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr;
|
|
return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
|
|
}
|
|
case ISD::MULHU:
|
|
case ISD::MULHS: {
|
|
// FIXME: Handle mul by immediate.
|
|
SDOperand MulLHS = Select(N->getOperand(0));
|
|
SDOperand MulRHS = Select(N->getOperand(1));
|
|
unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr;
|
|
SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
|
|
MulLHS, MulRHS);
|
|
// The high part is in the Y register.
|
|
return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1));
|
|
}
|
|
case ISD::CALL:
|
|
// FIXME: This is a workaround for a bug in tblgen.
|
|
{ // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag)
|
|
// Emits: (CALL:void (tglobaladdr:i32):$dst)
|
|
// Pattern complexity = 2 cost = 1
|
|
SDOperand N1 = N->getOperand(1);
|
|
if (N1.getOpcode() != ISD::TargetGlobalAddress &&
|
|
N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail;
|
|
SDOperand InFlag = SDOperand(0, 0);
|
|
SDOperand Chain = N->getOperand(0);
|
|
SDOperand Tmp0 = N1;
|
|
Chain = Select(Chain);
|
|
SDOperand Result;
|
|
if (N->getNumOperands() == 3) {
|
|
InFlag = Select(N->getOperand(2));
|
|
Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0,
|
|
Chain, InFlag);
|
|
} else {
|
|
Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0,
|
|
Chain);
|
|
}
|
|
Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0);
|
|
CodeGenMap[SDOperand(N, 1)] = Result.getValue(1);
|
|
return Result.getValue(Op.ResNo);
|
|
}
|
|
P47Fail:;
|
|
|
|
}
|
|
|
|
return SelectCode(Op);
|
|
}
|
|
|
|
|
|
/// createPPCISelDag - This pass converts a legalized DAG into a
|
|
/// PowerPC-specific DAG, ready for instruction scheduling.
|
|
///
|
|
FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
|
|
return new SparcV8DAGToDAGISel(TM);
|
|
}
|