Tim Northover a10c01a6c6 ARM: relax the atomic release barrier to "dmb ishst" on Swift ... Swift cores implement store barriers that are stronger than the ARM specification but weaker than general barriers. They are, in fact, just about enough to provide the ordering needed for atomic operations with release semantics. This patch makes use of that quirk. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185527 91177308-0d34-0410-b5e6-96231b3b80d8		2013-07-03 09:20:36 +00:00
..
AArch64	AArch64: correct CodeGen of MOVZ/MOVK combinations.	2013-07-01 19:23:10 +00:00
ARM	ARM: relax the atomic release barrier to "dmb ishst" on Swift	2013-07-03 09:20:36 +00:00
CPP
Generic	Debug Info: clean up usage of Verify.	2013-06-28 05:43:10 +00:00
Hexagon	Hexagon: Pass to replace tranfer/copy instructions into combine instruction	2013-05-14 18:54:06 +00:00
Inputs
MBlaze
Mips	[mips] Fix test case to check that mips64 instructions are generated.	2013-07-01 20:18:58 +00:00
MSP430	Really fix the test. Sorry for the breakage...	2013-07-01 19:51:36 +00:00
NVPTX	[NVPTX] Add support for module-scope inline asm	2013-07-01 13:00:14 +00:00
PowerPC	[PowerPC] Remove VK_PPC_TLSGD and VK_PPC_TLSLD	2013-07-02 21:29:06 +00:00
R600	R600: Support schedule and packetization of trans-only inst	2013-06-29 19:32:43 +00:00
SI
SPARC	Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo.	2013-06-17 19:00:36 +00:00
SystemZ	[SystemZ] Use DSGFR over DSGR in more cases	2013-07-02 15:40:22 +00:00
Thumb	LocalStackSlotAllocation improvements	2013-04-30 20:04:37 +00:00
Thumb2	ARM: allow predicated barriers in Thumb mode	2013-06-26 16:52:32 +00:00
X86	DAGCombiner: fix use-counting issue when forming zextload	2013-07-02 09:58:53 +00:00
XCore	[XCore] Add ISel pattern for LDWCP	2013-07-03 07:48:50 +00:00