llvm-6502/lib/Target/Sparc
Dan Gohman b8275a3f6f Don't ignore the return value of AsmPrinter::doInitialization and
AsmPrinter::doFinalization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40487 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-25 19:33:14 +00:00
..
DelaySlotFiller.cpp Drop 'const' 2007-05-03 01:11:54 +00:00
FPMover.cpp Drop 'const' 2007-05-03 01:11:54 +00:00
Makefile don't dist internal readme 2006-10-28 00:51:15 +00:00
README.txt
Sparc.h silence warnings 2006-11-03 01:11:05 +00:00
Sparc.td
SparcAsmPrinter.cpp Don't ignore the return value of AsmPrinter::doInitialization and 2007-07-25 19:33:14 +00:00
SparcInstrFormats.td Change instruction description to split OperandList into OutOperandList and 2007-07-19 01:14:50 +00:00
SparcInstrInfo.cpp RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. 2007-05-18 00:18:17 +00:00
SparcInstrInfo.h RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. 2007-05-18 00:18:17 +00:00
SparcInstrInfo.td No more noResults. 2007-07-21 00:34:19 +00:00
SparcISelDAGToDAG.cpp Fix CodeGen/Generic/print-arith-fp.ll on sparc (PR1551) 2007-07-13 16:24:10 +00:00
SparcRegisterInfo.cpp Long live the exception handling! 2007-07-14 14:06:15 +00:00
SparcRegisterInfo.h Long live the exception handling! 2007-07-14 14:06:15 +00:00
SparcRegisterInfo.td Fix for PR1540: Specify F0, F1 are sub-registers of D0, etc. 2007-07-13 23:55:50 +00:00
SparcSubtarget.cpp Patches to make the LLVM sources more -pedantic clean. Patch provided 2006-05-24 17:04:05 +00:00
SparcSubtarget.h
SparcTargetAsmInfo.cpp Break out target asm info into separate files. 2006-09-07 22:05:02 +00:00
SparcTargetAsmInfo.h Break out target asm info into separate files. 2006-09-07 22:05:02 +00:00
SparcTargetMachine.cpp Fix an oversight: for modules with no other identifying target info, 2007-07-11 16:32:10 +00:00
SparcTargetMachine.h 1. Remove condition on delete. 2006-09-07 23:39:26 +00:00

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots