Andrew Trick b86a0cdb67 Machine Model: Add MicroOpBufferSize and resource BufferSize. ... Replace the ill-defined MinLatency and ILPWindow properties with with straightforward buffer sizes: MCSchedMode::MicroOpBufferSize MCProcResourceDesc::BufferSize These can be used to more precisely model instruction execution if desired. Disabled some misched tests temporarily. They'll be reenabled in a few commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184032 91177308-0d34-0410-b5e6-96231b3b80d8		2013-06-15 04:49:57 +00:00
..
AArch64	Change how we iterate over relocations on ELF.	2013-05-30 03:05:14 +00:00
ARM	Make PrologEpilogInserter save/restore all callee saved registers	2013-06-14 16:15:29 +00:00
CPP
Generic
Hexagon
Inputs
MBlaze
Mips	[mips] Add an IR transformation pass that optimizes calls to sqrt.	2013-06-11 22:21:44 +00:00
MSP430
NVPTX	[NVPTX] Remove old CONST_NOT_GEN address space that is not being used anymore and causes constants to be emitted in the global address space	2013-06-10 13:29:47 +00:00
PowerPC	[PowerPC] Disable fast-isel for existing -O0 tests for PowerPC.	2013-06-13 20:23:34 +00:00
R600	R600: Add SI load support for v[24]i32 and store for v2i32	2013-06-15 00:09:31 +00:00
SI
SPARC	[Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend.	2013-06-08 15:32:59 +00:00
SystemZ	[SystemZ] Don't use LOAD and STORE REVERSED for volatile accesses	2013-05-31 13:25:22 +00:00
Thumb
Thumb2	Cortex-R5 can issue Thumb2 integer division instructions.	2013-06-04 22:52:09 +00:00
X86	Machine Model: Add MicroOpBufferSize and resource BufferSize.	2013-06-15 04:49:57 +00:00
XCore