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https://github.com/c64scene-ar/llvm-6502.git
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46090914b7
mips16/mips32 floating point interoperability. This patch fixes returns from mips16 functions so that if the function was in fact called by a mips32 hard float routine, then values that would have been returned in floating point registers are so returned. Mips16 mode has no floating point instructions so there is no way to load values into floating point registers. This is needed when returning float, double, single complex, double complex in the Mips ABI. Helper functions in libc for mips16 are available to do this. For efficiency purposes, these helper functions have a different calling convention from normal Mips calls. Registers v0,v1,a0,a1 are used to pass parameters instead of a0,a1,a2,a3. This is because v0,v1,a0,a1 are the natural registers used to return floating point values in soft float. These values can then be moved to the appropriate floating point registers with no extra cost. The only register that is modified is ra in this call. The helper functions make sure that the return values are in the floating point registers that they would be in if soft float was not in effect (which it is for mips16, though the soft float is implemented using a mips32 library that uses hard float). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181641 91177308-0d34-0410-b5e6-96231b3b80d8
84 lines
2.7 KiB
C++
84 lines
2.7 KiB
C++
//===-- MipsRegisterInfo.h - Mips Register Information Impl -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef MIPSREGISTERINFO_H
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#define MIPSREGISTERINFO_H
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#include "Mips.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#define GET_REGINFO_HEADER
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#include "MipsGenRegisterInfo.inc"
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namespace llvm {
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class MipsSubtarget;
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class Type;
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class MipsRegisterInfo : public MipsGenRegisterInfo {
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protected:
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const MipsSubtarget &Subtarget;
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public:
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MipsRegisterInfo(const MipsSubtarget &Subtarget);
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/// getRegisterNumbering - Given the enum value for some register, e.g.
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/// Mips::RA, return the number that it corresponds to (e.g. 31).
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static unsigned getRegisterNumbering(unsigned RegEnum);
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/// Get PIC indirect call register
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static unsigned getPICCallReg();
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/// Adjust the Mips stack frame.
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void adjustMipsStackFrame(MachineFunction &MF) const;
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/// Code Generation virtual methods...
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unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const;
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const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
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const uint32_t *getCallPreservedMask(CallingConv::ID) const;
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static const uint32_t *getMips16RetHelperMask();
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BitVector getReservedRegs(const MachineFunction &MF) const;
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virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
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virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const;
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/// Stack Frame Processing Methods
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void eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS = NULL) const;
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void processFunctionBeforeFrameFinalized(MachineFunction &MF,
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RegScavenger *RS = NULL) const;
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/// Debug information queries.
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unsigned getFrameRegister(const MachineFunction &MF) const;
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/// Exception handling queries.
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unsigned getEHExceptionRegister() const;
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unsigned getEHHandlerRegister() const;
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/// \brief Return GPR register class.
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virtual const TargetRegisterClass *intRegClass(unsigned Size) const = 0;
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private:
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virtual void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo,
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int FrameIndex, uint64_t StackSize,
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int64_t SPOffset) const = 0;
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};
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} // end namespace llvm
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#endif
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