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Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
151 lines
4.9 KiB
C++
151 lines
4.9 KiB
C++
//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that Mips uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef MipsISELLOWERING_H
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#define MipsISELLOWERING_H
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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#include "Mips.h"
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#include "MipsSubtarget.h"
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namespace llvm {
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namespace MipsISD {
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enum NodeType {
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// Start the numbering from where ISD NodeType finishes.
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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// Jump and link (call)
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JmpLink,
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// Get the Higher 16 bits from a 32-bit immediate
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// No relation with Mips Hi register
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Hi,
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// Get the Lower 16 bits from a 32-bit immediate
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// No relation with Mips Lo register
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Lo,
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// Handle gp_rel (small data/bss sections) relocation.
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GPRel,
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// Conditional Move
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CMov,
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// Select CC Pseudo Instruction
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SelectCC,
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// Floating Point Select CC Pseudo Instruction
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FPSelectCC,
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// Floating Point Branch Conditional
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FPBrcond,
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// Floating Point Compare
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FPCmp,
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// Floating Point Rounding
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FPRound,
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// Return
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Ret
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};
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}
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//===--------------------------------------------------------------------===//
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// TargetLowering Implementation
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//===--------------------------------------------------------------------===//
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class MipsTargetLowering : public TargetLowering
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{
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public:
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explicit MipsTargetLowering(MipsTargetMachine &TM);
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/// LowerOperation - Provide custom lowering hooks for some operations.
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
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/// getTargetNodeName - This method returns the name of a target specific
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// DAG node.
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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/// getSetCCResultType - get the ISD::SETCC result ValueType
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MVT getSetCCResultType(MVT VT) const;
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/// getFunctionAlignment - Return the Log2 alignment of this function.
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virtual unsigned getFunctionAlignment(const Function *F) const;
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private:
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// Subtarget Info
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const MipsSubtarget *Subtarget;
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// Lower Operand helpers
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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unsigned CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals);
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// Lower Operand specifics
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SDValue LowerANDOR(SDValue Op, SelectionDAG &DAG);
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SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG);
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SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
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SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG);
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SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG);
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
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SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
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SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
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SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG);
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
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virtual SDValue
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LowerFormalArguments(SDValue Chain,
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unsigned CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals);
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virtual SDValue
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LowerCall(SDValue Chain, SDValue Callee,
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unsigned CallConv, bool isVarArg,
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bool isTailCall,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals);
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virtual SDValue
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LowerReturn(SDValue Chain,
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unsigned CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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DebugLoc dl, SelectionDAG &DAG);
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virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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// Inline asm support
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ConstraintType getConstraintType(const std::string &Constraint) const;
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint,
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MVT VT) const;
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std::vector<unsigned>
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getRegClassForInlineAsmConstraint(const std::string &Constraint,
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MVT VT) const;
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virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
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};
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}
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#endif // MipsISELLOWERING_H
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