mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7cbd525ba8
fixme from the PowerPC backend. Emit slightly better code for legalizing select_cc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22805 91177308-0d34-0410-b5e6-96231b3b80d8
544 lines
17 KiB
C++
544 lines
17 KiB
C++
#if 0
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//===- SparcV8ISelPattern.cpp - A pattern matching isel for SparcV8 -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a pattern matching instruction selector for SparcV8.
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//
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//===----------------------------------------------------------------------===//
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//Please note that this file is a work in progress, and not a high
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//priority for anyone.
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#include "SparcV8.h"
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#include "SparcV8RegisterInfo.h"
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#include "llvm/Constants.h" // FIXME: REMOVE
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineConstantPool.h" // FIXME: REMOVE
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/CommandLine.h"
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#include <set>
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#include <algorithm>
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// V8TargetLowering - SparcV8 Implementation of the TargetLowering interface
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namespace {
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class V8TargetLowering : public TargetLowering {
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int VarArgsFrameIndex; // FrameIndex for start of varargs area.
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public:
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V8TargetLowering(TargetMachine &TM) : TargetLowering(TM) {
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// Set up the TargetLowering object.
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//I am having problems with shr n ubyte 1
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setShiftAmountType(MVT::i32);
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setSetCCResultType(MVT::i32);
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setSetCCResultContents(ZeroOrOneSetCCResult);
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//FIXME: get these right
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addRegisterClass(MVT::i64, V8::GPRCRegisterClass);
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addRegisterClass(MVT::f64, V8::FPRCRegisterClass);
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addRegisterClass(MVT::f32, V8::FPRCRegisterClass);
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setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
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setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
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setOperationAction(ISD::EXTLOAD, MVT::i1, Promote);
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setOperationAction(ISD::EXTLOAD, MVT::f32, Promote);
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setOperationAction(ISD::ZEXTLOAD, MVT::i1, Expand);
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setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand);
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setOperationAction(ISD::UREM, MVT::i32, Expand);
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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setOperationAction(ISD::CTPOP, MVT::i32, Expand);
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setOperationAction(ISD::CTTZ, MVT::i32, Expand);
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setOperationAction(ISD::CTLZ, MVT::i32, Expand);
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setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
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setOperationAction(ISD::MEMSET, MVT::Other, Expand);
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setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
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// We don't support sin/cos/sqrt
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::FSQRT, MVT::f64, Expand);
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::FSQRT, MVT::f32, Expand);
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computeRegisterProperties();
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addLegalFPImmediate(+0.0); //F31
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addLegalFPImmediate(-0.0); //-F31
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}
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/// LowerArguments - This hook must be implemented to indicate how we should
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/// lower the arguments for the specified function, into the specified DAG.
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virtual std::vector<SDOperand>
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LowerArguments(Function &F, SelectionDAG &DAG);
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/// LowerCallTo - This hook lowers an abstract call to a function into an
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/// actual call.
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virtual std::pair<SDOperand, SDOperand>
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LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CC,
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bool isTailCall, SDOperand Callee, ArgListTy &Args,
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SelectionDAG &DAG);
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};
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}
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/// AddLiveIn - This helper function adds the specified physical register to the
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/// MachineFunction as a live in value. It also creates a corresponding virtual
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/// register for it.
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static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
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TargetRegisterClass *RC) {
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assert(RC->contains(PReg) && "Not the correct regclass!");
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unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
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MF.addLiveIn(PReg, VReg);
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return VReg;
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}
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std::vector<SDOperand>
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V8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
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{
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static const unsigned IncomingArgRegs[] =
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{ V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5 };
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std::vector<SDOperand> ArgValues;
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo*MFI = MF.getFrameInfo();
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MachineBasicBlock& BB = MF.front();
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unsigned ArgNo = 0;
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unsigned ArgOffset = 92;
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for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
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I != E; ++I, ++ArgNo) {
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MVT::ValueType VT = getValueType(I->getType());
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SDOperand argt;
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if (ArgNo < 6) {
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switch(VT) {
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default:
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std::cerr << "Unknown Type " << VT << "\n";
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abort();
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case MVT::f64:
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case MVT::i64:
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//FIXME: figure out the build pair thing
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assert(0 && "doubles and longs not supported yet");
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case MVT::f32:
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argt = DAG.getCopyFromReg(AddLiveIn(MF, IncomingArgRegs[ArgNo],
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MVT::i32),
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VT, DAG.getRoot());
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//copy out of Int reg
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argt = DAG.getNode(ISD::FP_TO_UINT, MVT::f32, argt);
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break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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argt = DAG.getCopyFromReg(AddLiveIn(MF, IncomingArgRegs[ArgNo],
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getRegClassFor(MVT::i32)),
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VT, DAG.getRoot());
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if (VT != MVT::i32)
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argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
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break;
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}
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DAG.setRoot(argt.getValue(1));
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} else {
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//stack passed
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switch(VT) {
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default:
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std::cerr << "Unknown Type " << VT << "\n";
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abort();
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case MVT::f64:
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case MVT::i64:
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//FIXME: figure out the build pair thing
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assert(0 && "doubles and longs not supported yet");
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case MVT::f32:
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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// Create the frame index object for this incoming parameter...
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int FI = MFI->CreateFixedObject(4, ArgOffset);
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argt = DAG.getLoad(VT,
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DAG.getEntryNode(),
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DAG.getFramIndex(FI, MVT::i32),
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DAG.getSrcValue(NULL));
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ArgOffset += 4;
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break;
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}
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ArgValues.push_back(argt);
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}
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}
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//return the arguments
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return ArgValues;
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}
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std::pair<SDOperand, SDOperand>
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V8TargetLowering::LowerCallTo(SDOperand Chain,
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const Type *RetTy, bool isVarArg,
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unsigned CallingConv, bool isTailCall,
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SDOperand Callee, ArgListTy &Args,
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SelectionDAG &DAG) {
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//FIXME
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return std::make_pair(Chain, Chain);
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}
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namespace {
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//===--------------------------------------------------------------------===//
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/// ISel - V8 specific code to select V8 machine instructions for
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/// SelectionDAG operations.
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//===--------------------------------------------------------------------===//
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class ISel : public SelectionDAGISel {
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/// V8Lowering - This object fully describes how to lower LLVM code to an
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/// V8-specific SelectionDAG.
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V8TargetLowering V8Lowering;
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SelectionDAG *ISelDAG; // Hack to support us having a dag->dag transform
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// for sdiv and udiv until it is put into the future
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// dag combiner.
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/// ExprMap - As shared expressions are codegen'd, we keep track of which
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/// vreg the value is produced in, so we only emit one copy of each compiled
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/// tree.
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static const unsigned notIn = (unsigned)(-1);
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std::map<SDOperand, unsigned> ExprMap;
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public:
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ISel(TargetMachine &TM) : SelectionDAGISel(V8Lowering), V8Lowering(TM)
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{}
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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// Codegen the basic block.
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ISelDAG = &DAG;
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max_depth = DAG.getRoot().getNodeDepth();
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Select(DAG.getRoot());
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// Clear state used for selection.
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ExprMap.clear();
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}
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virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
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unsigned SelectExpr(SDOperand N);
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void Select(SDOperand N);
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};
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}
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void ISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
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// If this function has live-in values, emit the copies from pregs to vregs at
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// the top of the function, before anything else.
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MachineBasicBlock *BB = MF.begin();
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if (MF.livein_begin() != MF.livein_end()) {
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SSARegMap *RegMap = MF.getSSARegMap();
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for (MachineFunction::livein_iterator LI = MF.livein_begin(),
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E = MF.livein_end(); LI != E; ++LI) {
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const TargetRegisterClass *RC = RegMap->getRegClass(LI->second);
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if (RC == V8::GPRCRegisterClass) {
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BuildMI(BB, V8::ORrr, 2, LI->second).addReg(LI->first).addReg(V8::G0);
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} else if (RC == V8::FPRCRegisterClass) {
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BuildMI(BB, V8::FMOVSrr, 2, LI->second).addReg(LI->first);
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} else {
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assert(0 && "Unknown regclass!");
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}
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}
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}
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}
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//These describe LDAx
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static const int IMM_LOW = -32768;
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static const int IMM_HIGH = 32767;
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static const int IMM_MULT = 65536;
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static long getUpper16(long l)
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{
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long y = l / IMM_MULT;
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if (l % IMM_MULT > IMM_HIGH)
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++y;
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return y;
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}
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static long getLower16(long l)
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{
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long h = getUpper16(l);
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return l - h * IMM_MULT;
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}
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unsigned ISel::SelectExpr(SDOperand N) {
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unsigned Result;
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unsigned Tmp1, Tmp2 = 0, Tmp3;
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unsigned Opc = 0;
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unsigned opcode = N.getOpcode();
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SDNode *Node = N.Val;
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MVT::ValueType DestType = N.getValueType();
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unsigned &Reg = ExprMap[N];
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if (Reg) return Reg;
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if (N.getOpcode() != ISD::CALL && N.getOpcode() != ISD::TAILCALL)
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Reg = Result = (N.getValueType() != MVT::Other) ?
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MakeReg(N.getValueType()) : notIn;
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else {
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// If this is a call instruction, make sure to prepare ALL of the result
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// values as well as the chain.
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if (Node->getNumValues() == 1)
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Reg = Result = notIn; // Void call, just a chain.
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else {
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Result = MakeReg(Node->getValueType(0));
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ExprMap[N.getValue(0)] = Result;
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for (unsigned i = 1, e = N.Val->getNumValues()-1; i != e; ++i)
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ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
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ExprMap[SDOperand(Node, Node->getNumValues()-1)] = notIn;
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}
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}
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switch (opcode) {
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default:
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Node->dump();
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assert(0 && "Node not handled!\n");
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case ISD::EXTLOAD:
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case ISD::ZEXTLOAD:
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case ISD::SEXTLOAD:
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case ISD::LOAD:
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{
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// Make sure we generate both values.
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if (Result != notIn)
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ExprMap[N.getValue(1)] = notIn; // Generate the token
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else
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Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
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SDOperand Chain = N.getOperand(0);
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SDOperand Address = N.getOperand(1);
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Select(Chain);
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unsigned Adr = SelectExpr(Address);
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switch(cast<VTSDNode>(Node->getOperand(3))->getVT()) {
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case MVT::i32: Opc = V8::LD;
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case MVT::i16: Opc = opcode == ISD::ZEXTLOAD ? V8::LDUH : V8::LDSH; break;
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case MVT::i8: Opc = opcode == ISD::ZEXTLOAD ? V8::LDUB : V8::LDSB; break;
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case MVT::f64: Opc = V8::LDFSRrr;
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case MVT::f32: Opc = V8::LDDFrr;
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default:
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Node->dump();
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assert(0 && "Bad type!");
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break;
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}
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BuildMI(BB, Opc, 1, Result).addReg(Adr);
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return Result;
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}
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case ISD::TAILCALL:
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case ISD::CALL:
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{
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//FIXME:
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abort();
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return Result;
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}
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case ISD::CopyFromReg:
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{
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// Make sure we generate both values.
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if (Result != notIn)
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ExprMap[N.getValue(1)] = notIn; // Generate the token
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else
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Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
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SDOperand Chain = N.getOperand(0);
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Select(Chain);
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unsigned r = dyn_cast<RegSDNode>(Node)->getReg();
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BuildMI(BB, V8::ORrr, 2, Result).addReg(r).addReg(V8::G0);
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return Result;
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}
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//Most of the plain arithmetic and logic share the same form, and the same
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//constant immediate test
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case ISD::XOR:
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case ISD::AND:
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case ISD::OR:
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case ISD::SHL:
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case ISD::SRL:
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case ISD::SRA:
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case ISD::ADD:
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case ISD::SUB:
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case ISD::SDIV:
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case ISD::UDIV:
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case ISD::SMUL:
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case ISD::UMUL:
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switch(opcode) {
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case ISD::XOR: Opc = V8::XORrr; break;
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case ISD::AND: Opc = V8::ANDrr; break;
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case ISD::OR: Opc = V8::ORrr; break;
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case ISD::SHL: Opc = V8::SLLrr; break;
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case ISD::SRL: Opc = V8::SRLrr; break;
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case ISD::SRA: Opc = V8::SRArr; break;
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case ISD::ADD: Opc = V8::ADDrr; break;
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case ISD::SUB: Opc = V8::SUBrr; break;
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case ISD::SDIV: Opc = V8::SDIVrr; break;
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case ISD::UDIV: Opc = V8::UDIVrr; break;
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case ISD::SMUL: Opc = V8::SMULrr; break;
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case ISD::UMUL: Opc = V8::UMULrr; break;
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}
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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return Result;
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}
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return 0;
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}
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void ISel::Select(SDOperand N) {
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unsigned Tmp1, Tmp2, Opc;
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unsigned opcode = N.getOpcode();
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if (!ExprMap.insert(std::make_pair(N, notIn)).second)
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return; // Already selected.
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SDNode *Node = N.Val;
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switch (opcode) {
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default:
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Node->dump(); std::cerr << "\n";
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assert(0 && "Node not handled yet!");
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case ISD::BRCOND: {
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//FIXME
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abort();
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return;
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}
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case ISD::BR: {
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MachineBasicBlock *Dest =
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cast<BasicBlockSDNode>(N.getOperand(1))->getBasicBlock();
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Select(N.getOperand(0));
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BuildMI(BB, V8::BA, 1).addMBB(Dest);
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return;
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}
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case ISD::ImplicitDef:
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Select(N.getOperand(0));
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BuildMI(BB, V8::IMPLICIT_DEF, 0, cast<RegSDNode>(N)->getReg());
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return;
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case ISD::EntryToken: return; // Noop
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case ISD::TokenFactor:
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for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
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Select(Node->getOperand(i));
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return;
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case ISD::CopyToReg:
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Select(N.getOperand(0));
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Tmp1 = SelectExpr(N.getOperand(1));
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Tmp2 = cast<RegSDNode>(N)->getReg();
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if (Tmp1 != Tmp2) {
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if (N.getOperand(1).getValueType() == MVT::f64 ||
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N.getOperand(1).getValueType() == MVT::f32)
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BuildMI(BB, V8::FMOVS, 2, Tmp2).addReg(Tmp1);
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else
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BuildMI(BB, V8::ORrr, 2, Tmp2).addReg(Tmp1).addReg(V8::G0);
|
|
}
|
|
return;
|
|
|
|
case ISD::RET:
|
|
//FIXME:
|
|
abort();
|
|
return;
|
|
|
|
case ISD::TRUNCSTORE:
|
|
case ISD::STORE:
|
|
{
|
|
SDOperand Chain = N.getOperand(0);
|
|
SDOperand Value = N.getOperand(1);
|
|
SDOperand Address = N.getOperand(2);
|
|
Select(Chain);
|
|
|
|
Tmp1 = SelectExpr(Value);
|
|
Tmp2 = SelectExpr(Address);
|
|
|
|
unsigned VT = opcode == ISD::STORE ?
|
|
Value.getValueType() : cast<VTSDNode>(Node->getOperand(4))->getVT();
|
|
switch(VT) {
|
|
default: assert(0 && "unknown Type in store");
|
|
case MVT::f64: Opc = V8::STDFrr; break;
|
|
case MVT::f32: Opc = V8::STFrr; break;
|
|
case MVT::i1: //FIXME: DAG does not promote this load
|
|
case MVT::i8: Opc = V8::STBrr; break;
|
|
case MVT::i16: Opc = V8::STHrr; break;
|
|
case MVT::i32: Opc = V8::STLrr; break;
|
|
case MVT::i64: Opc = V8::STDrr; break;
|
|
}
|
|
|
|
BuildMI(BB,Opc,2).addReg(Tmp1).addReg(Tmp2);
|
|
return;
|
|
}
|
|
|
|
case ISD::EXTLOAD:
|
|
case ISD::SEXTLOAD:
|
|
case ISD::ZEXTLOAD:
|
|
case ISD::LOAD:
|
|
case ISD::CopyFromReg:
|
|
case ISD::TAILCALL:
|
|
case ISD::CALL:
|
|
case ISD::DYNAMIC_STACKALLOC:
|
|
ExprMap.erase(N);
|
|
SelectExpr(N);
|
|
return;
|
|
|
|
case ISD::CALLSEQ_START:
|
|
case ISD::CALLSEQ_END:
|
|
Select(N.getOperand(0));
|
|
Tmp1 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
|
|
|
|
Opc = N.getOpcode() == ISD::CALLSEQ_START ? V8::ADJUSTCALLSTACKDOWN :
|
|
V8::ADJUSTCALLSTACKUP;
|
|
BuildMI(BB, Opc, 1).addImm(Tmp1);
|
|
return;
|
|
}
|
|
assert(0 && "Should not be reached!");
|
|
}
|
|
|
|
|
|
/// createV8PatternInstructionSelector - This pass converts an LLVM function
|
|
/// into a machine code representation using pattern matching and a machine
|
|
/// description file.
|
|
///
|
|
FunctionPass *llvm::createV8PatternInstructionSelector(TargetMachine &TM) {
|
|
return new ISel(TM);
|
|
}
|
|
|
|
#endif
|