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b1d081230e
The parser will now accept instructions with alignment specifiers written like
vld1.8 {d16}, [r0:64]
, while also still accepting the incorrect syntax
vld1.8 {d16}, [r0, :64]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175164 91177308-0d34-0410-b5e6-96231b3b80d8
14 lines
834 B
Plaintext
14 lines
834 B
Plaintext
# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
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# Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# -------------------------------------------------------------------------------------------------
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# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 1: 0| 0: 0: 1: 0| 1: 1: 1: 1|
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# -------------------------------------------------------------------------------------------------
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#
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# A8.6.391 VST1 (multiple single elements)
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# This encoding looks like: vst1.8 {d0,d1,d2}, [r0:128]
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# But bits 5-4 for the alignment of 128 encoded as align = 0b10, is available only if <list>
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# contains two or four registers. rdar://11220250
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0x00 0xf9 0x2f 0x06
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