mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-01 15:11:24 +00:00
0305dd745e
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83616 91177308-0d34-0410-b5e6-96231b3b80d8
342 lines
12 KiB
LLVM
342 lines
12 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vsras8:
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;CHECK: vsra.s8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = ashr <8 x i8> %tmp2, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
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%tmp4 = add <8 x i8> %tmp1, %tmp3
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ret <8 x i8> %tmp4
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}
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define <4 x i16> @vsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vsras16:
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;CHECK: vsra.s16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = ashr <4 x i16> %tmp2, < i16 16, i16 16, i16 16, i16 16 >
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%tmp4 = add <4 x i16> %tmp1, %tmp3
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ret <4 x i16> %tmp4
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}
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define <2 x i32> @vsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vsras32:
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;CHECK: vsra.s32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = ashr <2 x i32> %tmp2, < i32 32, i32 32 >
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%tmp4 = add <2 x i32> %tmp1, %tmp3
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ret <2 x i32> %tmp4
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}
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define <1 x i64> @vsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
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;CHECK: vsras64:
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;CHECK: vsra.s64
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%tmp1 = load <1 x i64>* %A
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%tmp2 = load <1 x i64>* %B
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%tmp3 = ashr <1 x i64> %tmp2, < i64 64 >
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%tmp4 = add <1 x i64> %tmp1, %tmp3
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ret <1 x i64> %tmp4
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}
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define <16 x i8> @vsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK: vsraQs8:
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;CHECK: vsra.s8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = ashr <16 x i8> %tmp2, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
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%tmp4 = add <16 x i8> %tmp1, %tmp3
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ret <16 x i8> %tmp4
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}
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define <8 x i16> @vsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vsraQs16:
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;CHECK: vsra.s16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = ashr <8 x i16> %tmp2, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
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%tmp4 = add <8 x i16> %tmp1, %tmp3
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vsraQs32:
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;CHECK: vsra.s32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = ashr <4 x i32> %tmp2, < i32 32, i32 32, i32 32, i32 32 >
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%tmp4 = add <4 x i32> %tmp1, %tmp3
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ret <4 x i32> %tmp4
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}
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define <2 x i64> @vsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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;CHECK: vsraQs64:
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;CHECK: vsra.s64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%tmp3 = ashr <2 x i64> %tmp2, < i64 64, i64 64 >
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%tmp4 = add <2 x i64> %tmp1, %tmp3
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ret <2 x i64> %tmp4
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}
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define <8 x i8> @vsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vsrau8:
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;CHECK: vsra.u8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = lshr <8 x i8> %tmp2, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
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%tmp4 = add <8 x i8> %tmp1, %tmp3
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ret <8 x i8> %tmp4
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}
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define <4 x i16> @vsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vsrau16:
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;CHECK: vsra.u16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = lshr <4 x i16> %tmp2, < i16 16, i16 16, i16 16, i16 16 >
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%tmp4 = add <4 x i16> %tmp1, %tmp3
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ret <4 x i16> %tmp4
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}
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define <2 x i32> @vsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vsrau32:
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;CHECK: vsra.u32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = lshr <2 x i32> %tmp2, < i32 32, i32 32 >
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%tmp4 = add <2 x i32> %tmp1, %tmp3
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ret <2 x i32> %tmp4
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}
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define <1 x i64> @vsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
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;CHECK: vsrau64:
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;CHECK: vsra.u64
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%tmp1 = load <1 x i64>* %A
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%tmp2 = load <1 x i64>* %B
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%tmp3 = lshr <1 x i64> %tmp2, < i64 64 >
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%tmp4 = add <1 x i64> %tmp1, %tmp3
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ret <1 x i64> %tmp4
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}
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define <16 x i8> @vsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK: vsraQu8:
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;CHECK: vsra.u8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = lshr <16 x i8> %tmp2, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
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%tmp4 = add <16 x i8> %tmp1, %tmp3
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ret <16 x i8> %tmp4
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}
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define <8 x i16> @vsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vsraQu16:
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;CHECK: vsra.u16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = lshr <8 x i16> %tmp2, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
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%tmp4 = add <8 x i16> %tmp1, %tmp3
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vsraQu32:
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;CHECK: vsra.u32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = lshr <4 x i32> %tmp2, < i32 32, i32 32, i32 32, i32 32 >
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%tmp4 = add <4 x i32> %tmp1, %tmp3
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ret <4 x i32> %tmp4
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}
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define <2 x i64> @vsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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;CHECK: vsraQu64:
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;CHECK: vsra.u64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%tmp3 = lshr <2 x i64> %tmp2, < i64 64, i64 64 >
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%tmp4 = add <2 x i64> %tmp1, %tmp3
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ret <2 x i64> %tmp4
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}
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define <8 x i8> @vrsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vrsras8:
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;CHECK: vrsra.s8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
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%tmp4 = add <8 x i8> %tmp1, %tmp3
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ret <8 x i8> %tmp4
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}
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define <4 x i16> @vrsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vrsras16:
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;CHECK: vrsra.s16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
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%tmp4 = add <4 x i16> %tmp1, %tmp3
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ret <4 x i16> %tmp4
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}
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define <2 x i32> @vrsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vrsras32:
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;CHECK: vrsra.s32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >)
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%tmp4 = add <2 x i32> %tmp1, %tmp3
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ret <2 x i32> %tmp4
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}
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define <1 x i64> @vrsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
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;CHECK: vrsras64:
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;CHECK: vrsra.s64
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%tmp1 = load <1 x i64>* %A
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%tmp2 = load <1 x i64>* %B
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%tmp3 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp2, <1 x i64> < i64 -64 >)
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%tmp4 = add <1 x i64> %tmp1, %tmp3
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ret <1 x i64> %tmp4
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}
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define <8 x i8> @vrsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vrsrau8:
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;CHECK: vrsra.u8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
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%tmp4 = add <8 x i8> %tmp1, %tmp3
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ret <8 x i8> %tmp4
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}
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define <4 x i16> @vrsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vrsrau16:
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;CHECK: vrsra.u16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
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%tmp4 = add <4 x i16> %tmp1, %tmp3
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ret <4 x i16> %tmp4
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}
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define <2 x i32> @vrsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vrsrau32:
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;CHECK: vrsra.u32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >)
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%tmp4 = add <2 x i32> %tmp1, %tmp3
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ret <2 x i32> %tmp4
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}
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define <1 x i64> @vrsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
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;CHECK: vrsrau64:
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;CHECK: vrsra.u64
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%tmp1 = load <1 x i64>* %A
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%tmp2 = load <1 x i64>* %B
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%tmp3 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp2, <1 x i64> < i64 -64 >)
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%tmp4 = add <1 x i64> %tmp1, %tmp3
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ret <1 x i64> %tmp4
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}
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define <16 x i8> @vrsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK: vrsraQs8:
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;CHECK: vrsra.s8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
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%tmp4 = add <16 x i8> %tmp1, %tmp3
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ret <16 x i8> %tmp4
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}
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define <8 x i16> @vrsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vrsraQs16:
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;CHECK: vrsra.s16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
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%tmp4 = add <8 x i16> %tmp1, %tmp3
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vrsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vrsraQs32:
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;CHECK: vrsra.s32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
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%tmp4 = add <4 x i32> %tmp1, %tmp3
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ret <4 x i32> %tmp4
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}
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define <2 x i64> @vrsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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;CHECK: vrsraQs64:
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;CHECK: vrsra.s64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%tmp3 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >)
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%tmp4 = add <2 x i64> %tmp1, %tmp3
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ret <2 x i64> %tmp4
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}
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define <16 x i8> @vrsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK: vrsraQu8:
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;CHECK: vrsra.u8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
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%tmp4 = add <16 x i8> %tmp1, %tmp3
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ret <16 x i8> %tmp4
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}
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define <8 x i16> @vrsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vrsraQu16:
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;CHECK: vrsra.u16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
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%tmp4 = add <8 x i16> %tmp1, %tmp3
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vrsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vrsraQu32:
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;CHECK: vrsra.u32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
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%tmp4 = add <4 x i32> %tmp1, %tmp3
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ret <4 x i32> %tmp4
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}
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define <2 x i64> @vrsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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;CHECK: vrsraQu64:
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;CHECK: vrsra.u64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%tmp3 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >)
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%tmp4 = add <2 x i64> %tmp1, %tmp3
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ret <2 x i64> %tmp4
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}
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declare <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
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declare <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
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declare <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
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declare <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
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declare <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
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