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f98f2ce29e
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
170 lines
6.5 KiB
C++
170 lines
6.5 KiB
C++
//===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Interface definition for R600InstrInfo
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//
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//===----------------------------------------------------------------------===//
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#ifndef R600INSTRUCTIONINFO_H_
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#define R600INSTRUCTIONINFO_H_
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#include "AMDIL.h"
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#include "AMDGPUInstrInfo.h"
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#include "R600Defines.h"
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#include "R600RegisterInfo.h"
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#include <map>
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namespace llvm {
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class AMDGPUTargetMachine;
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class DFAPacketizer;
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class ScheduleDAG;
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class MachineFunction;
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class MachineInstr;
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class MachineInstrBuilder;
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class R600InstrInfo : public AMDGPUInstrInfo {
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private:
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const R600RegisterInfo RI;
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int getBranchInstr(const MachineOperand &op) const;
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public:
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explicit R600InstrInfo(AMDGPUTargetMachine &tm);
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const R600RegisterInfo &getRegisterInfo() const;
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const;
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bool isTrig(const MachineInstr &MI) const;
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bool isPlaceHolderOpcode(unsigned opcode) const;
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bool isReductionOp(unsigned opcode) const;
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bool isCubeOp(unsigned opcode) const;
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/// \returns true if this \p Opcode represents an ALU instruction.
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bool isALUInstr(unsigned Opcode) const;
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/// \breif Vector instructions are instructions that must fill all
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/// instruction slots within an instruction group.
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bool isVector(const MachineInstr &MI) const;
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virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
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int64_t Imm) const;
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virtual unsigned getIEQOpcode() const;
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virtual bool isMov(unsigned Opcode) const;
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DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
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const ScheduleDAG *DAG) const;
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
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unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
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unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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bool isPredicated(const MachineInstr *MI) const;
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bool isPredicable(MachineInstr *MI) const;
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bool
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isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
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const BranchProbability &Probability) const;
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bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
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unsigned ExtraPredCycles,
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const BranchProbability &Probability) const ;
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bool
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isProfitableToIfCvt(MachineBasicBlock &TMBB,
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unsigned NumTCycles, unsigned ExtraTCycles,
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MachineBasicBlock &FMBB,
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unsigned NumFCycles, unsigned ExtraFCycles,
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const BranchProbability &Probability) const;
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bool DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const;
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bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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const SmallVectorImpl<MachineOperand> &Pred2) const;
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bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
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MachineBasicBlock &FMBB) const;
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bool PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const;
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unsigned int getInstrLatency(const InstrItineraryData *ItinData,
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const MachineInstr *MI,
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unsigned *PredCost = 0) const;
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virtual int getInstrLatency(const InstrItineraryData *ItinData,
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SDNode *Node) const { return 1;}
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/// You can use this function to avoid manually specifying each instruction
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/// modifier operand when building a new instruction.
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///
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/// \returns a MachineInstr with all the instruction modifiers initialized
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/// to their default values.
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MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned Opcode,
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unsigned DstReg,
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unsigned Src0Reg,
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unsigned Src1Reg = 0) const;
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MachineInstr *buildMovImm(MachineBasicBlock &BB,
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MachineBasicBlock::iterator I,
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unsigned DstReg,
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uint64_t Imm) const;
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/// \brief Get the index of Op in the MachineInstr.
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///
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/// \returns -1 if the Instruction does not contain the specified \p Op.
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int getOperandIdx(const MachineInstr &MI, R600Operands::Ops Op) const;
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/// \brief Get the index of \p Op for the given Opcode.
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///
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/// \returns -1 if the Instruction does not contain the specified \p Op.
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int getOperandIdx(unsigned Opcode, R600Operands::Ops Op) const;
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/// \brief Helper function for setting instruction flag values.
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void setImmOperand(MachineInstr *MI, R600Operands::Ops Op, int64_t Imm) const;
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/// \returns true if this instruction has an operand for storing target flags.
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bool hasFlagOperand(const MachineInstr &MI) const;
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///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
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void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
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///\brief Determine if the specified \p Flag is set on this \p Operand.
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bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
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/// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
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/// \param Flag The flag being set.
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///
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/// \returns the operand containing the flags for this instruction.
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MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
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unsigned Flag = 0) const;
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/// \brief Clear the specified flag on the instruction.
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void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
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};
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} // End llvm namespace
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#endif // R600INSTRINFO_H_
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