llvm-6502/test/CodeGen
David Peixotto b92cca2228 Fix PR18345: ldr= pseudo instruction produces incorrect code when using in inline assembly
This patch fixes the ldr-pseudo implementation to work when used in
inline assembly.  The fix is to move arm assembler constant pools
from the ARMAsmParser class to the ARMTargetStreamer class.

Previously we kept the assembler generated constant pools in the
ARMAsmParser object. This does not work for inline assembly because
a new parser object is created for each blob of inline assembly.
This patch moves the constant pools to the ARMTargetStreamer class
so that the constant pool will remain alive for the entire code
generation process.

An ARMTargetStreamer class is now required for the arm backend.
There was no existing implementation for MachO, only Asm and ELF.
Instead of creating an empty MachO subclass, we decided to make the
ARMTargetStreamer a non-abstract class and provide default
(llvm_unreachable) implementations for the non constant-pool related
methods.

Differential Revision: http://llvm-reviews.chandlerc.com/D2638


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200777 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-04 17:22:40 +00:00
..
AArch64 ARM & AArch64: merge NEON absolute compare intrinsics 2014-02-04 14:55:42 +00:00
ARM Fix PR18345: ldr= pseudo instruction produces incorrect code when using in inline assembly 2014-02-04 17:22:40 +00:00
CPP
Generic Additional fix for 200201: due to dependence on bitwidth test was moved to X86 directory. 2014-01-27 09:43:10 +00:00
Hexagon DebugInfo: Remove some unneeded conditionals now that DIBuilder no longer emits zero-length arrays as {i32 0} 2014-02-04 01:23:52 +00:00
Inputs
Mips [mips][msa] Add insert.d instruction. 2014-01-31 13:31:20 +00:00
MSP430 Fix known typos 2014-01-24 17:20:08 +00:00
NVPTX [NVPTX] Fix emitting aggregate parameters 2014-01-28 18:35:29 +00:00
PowerPC DebugInfo: Remove some unneeded conditionals now that DIBuilder no longer emits zero-length arrays as {i32 0} 2014-02-04 01:23:52 +00:00
R600 R600/SI: Custom lower i64 ISD::SELECT 2014-02-04 17:18:40 +00:00
SPARC [Sparc] Set %o7 as the return address register instead of %i7 in MCRegisterInfo. Also, add CFI instructions to initialize the frame correctly. 2014-02-01 18:54:16 +00:00
SystemZ XFAIL test/CodeGen/SystemZ/alias-01.ll which requires CodeGen TBAA 2014-01-25 19:31:44 +00:00
Thumb CodeGen: Stop treating vectors as aggregates 2014-01-21 22:46:46 +00:00
Thumb2 PGO branch weight: update edge weights in IfConverter. 2014-01-29 23:18:47 +00:00
X86 DebugInfo: Remove some unneeded conditionals now that DIBuilder no longer emits zero-length arrays as {i32 0} 2014-02-04 01:23:52 +00:00
XCore