llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-23 05:29:23 +00:00

History

Andrew Trick b961a26cec Allow MachineCSE to coalesce trivial subregister copies the same way

that it coalesces normal copies.

Without this, MachineCSE is powerless to handle redundant operations
with truncated source operands.

This required fixing the 2-addr pass to handle tied subregisters. It
isn't clear what combinations of subregisters can legally be tied, but
the simple case of truncated source operands is now safely handled:

     %vreg11<def> = COPY %vreg1:sub_32bit; GR32:%vreg11 GR64:%vreg1
     %vreg12<def> = COPY %vreg2:sub_32bit; GR32:%vreg12 GR64:%vreg2
     %vreg13<def,tied1> = ADD32rr %vreg11<tied0>, %vreg12<kill>, %EFLAGS<imp-def>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197414 91177308-0d34-0410-b5e6-96231b3b80d8

2013-12-16 19:36:21 +00:00

Analysis

[block-freq] Teach branch probability how to return the edge weight in between a BasicBlock and one of its successors.

2013-12-14 02:24:25 +00:00

AsmParser

Debug Info: drop debug info via upgrading path if version number does not match.

2013-12-02 21:29:56 +00:00

Bitcode

Remove unused value.

2013-12-07 02:27:52 +00:00

CodeGen

Allow MachineCSE to coalesce trivial subregister copies the same way