Tom Stellard 54a2540fee R600/SI: Use VALU for i1 XOR ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213528 91177308-0d34-0410-b5e6-96231b3b80d8		2014-07-21 14:01:10 +00:00
..
AArch64	CodeGen: emit IR-level f16 conversion intrinsics as fptrunc/fpext	2014-07-21 09:13:56 +00:00
ARM	ARM: correct WoA __builtin_alloca handling on O0	2014-07-19 01:29:51 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[mips] Do not emit '.module [no]oddspreg' unless we really need to.	2014-07-21 10:45:47 +00:00
MSP430
NVPTX	Add tests for atomic adds on floats.	2014-07-18 20:11:26 +00:00
PowerPC	[PowerPC] ELFv2 aggregate passing support	2014-07-21 00:13:26 +00:00
R600	R600/SI: Use VALU for i1 XOR	2014-07-21 14:01:10 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86	FileCheck-ize a test.	2014-07-21 09:23:21 +00:00
XCore	llvm/test/CodeGen/XCore/dwarf_debug.ll: Fix not to be affected by *-win32.	2014-07-04 11:58:03 +00:00