Matthias Braun c8fe2bf3a4 ARM: Enable MachineScheduler and disable PostRAScheduler for swift. ... This is mostly done to disable the PostRAScheduler which optimizes for instruction latencies which isn't a good fit for out-of-order architectures. This also allows to leave out the itinerary table in swift in favor of the SchedModel ones. This change leads to performance improvements/regressions by as much as 10% in some benchmarks, in fact we loose 0.4% performance over the llvm-testsuite for reasons that appear to be unknown or out of the compilers control. rdar://20803802 documents the investigation of these effects. While it is probably a good idea to perform the same switch for the other ARM out-of-order CPUs, I limited this change to swift as I cannot perform the benchmark verification on the other CPUs. Differential Revision: http://reviews.llvm.org/D10513 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242500 91177308-0d34-0410-b5e6-96231b3b80d8		2015-07-17 01:44:31 +00:00
..
llvm	ARM: Enable MachineScheduler and disable PostRAScheduler for swift.	2015-07-17 01:44:31 +00:00
llvm-c	Revert "Update LLVM bindings after r239940. ..."	2015-07-16 01:16:39 +00:00