mirror of
https://github.com/c64scene-ar/llvm-6502.git
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ba249e41f3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75941 91177308-0d34-0410-b5e6-96231b3b80d8
408 lines
15 KiB
C++
408 lines
15 KiB
C++
//===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the SystemZTargetLowering class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "systemz-lower"
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#include "SystemZISelLowering.h"
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#include "SystemZ.h"
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#include "SystemZTargetMachine.h"
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#include "SystemZSubtarget.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/CallingConv.h"
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#include "llvm/GlobalVariable.h"
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#include "llvm/GlobalAlias.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/VectorExtras.h"
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using namespace llvm;
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SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
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TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
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// Set up the register classes.
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addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
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addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
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// Compute derived properties from the register classes
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computeRegisterProperties();
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// Set shifts properties
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setShiftAmountFlavor(Extend);
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setShiftAmountType(MVT::i32);
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// Provide all sorts of operation actions
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setStackPointerRegisterToSaveRestore(SystemZ::R15D);
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setSchedulingPreference(SchedulingForLatency);
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setOperationAction(ISD::RET, MVT::Other, Custom);
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}
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SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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switch (Op.getOpcode()) {
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case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
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case ISD::RET: return LowerRET(Op, DAG);
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case ISD::CALL: return LowerCALL(Op, DAG);
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default:
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assert(0 && "unimplemented operand");
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return SDValue();
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}
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}
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//===----------------------------------------------------------------------===//
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// Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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#include "SystemZGenCallingConv.inc"
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SDValue SystemZTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
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SelectionDAG &DAG) {
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unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
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switch (CC) {
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default:
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assert(0 && "Unsupported calling convention");
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case CallingConv::C:
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case CallingConv::Fast:
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return LowerCCCArguments(Op, DAG);
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}
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}
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SDValue SystemZTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
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CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
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unsigned CallingConv = TheCall->getCallingConv();
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switch (CallingConv) {
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default:
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assert(0 && "Unsupported calling convention");
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case CallingConv::Fast:
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case CallingConv::C:
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return LowerCCCCallTo(Op, DAG, CallingConv);
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}
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}
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/// LowerCCCArguments - transform physical registers into virtual registers and
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/// generate load operations for arguments places on the stack.
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// FIXME: struct return stuff
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// FIXME: varargs
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SDValue SystemZTargetLowering::LowerCCCArguments(SDValue Op,
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SelectionDAG &DAG) {
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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SDValue Root = Op.getOperand(0);
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bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
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unsigned CC = MF.getFunction()->getCallingConv();
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DebugLoc dl = Op.getDebugLoc();
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// Assign locations to all of the incoming arguments.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
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CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_SystemZ);
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assert(!isVarArg && "Varargs not supported yet");
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SmallVector<SDValue, 16> ArgValues;
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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if (VA.isRegLoc()) {
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// Arguments passed in registers
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MVT RegVT = VA.getLocVT();
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switch (RegVT.getSimpleVT()) {
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default:
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cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
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<< RegVT.getSimpleVT()
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<< "\n";
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abort();
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case MVT::i64:
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unsigned VReg =
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RegInfo.createVirtualRegister(SystemZ::GR64RegisterClass);
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RegInfo.addLiveIn(VA.getLocReg(), VReg);
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SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
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// If this is an 8/16/32-bit value, it is really passed promoted to 64
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// bits. Insert an assert[sz]ext to capture this, then truncate to the
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// right size.
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if (VA.getLocInfo() == CCValAssign::SExt)
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ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
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DAG.getValueType(VA.getValVT()));
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else if (VA.getLocInfo() == CCValAssign::ZExt)
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ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
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DAG.getValueType(VA.getValVT()));
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if (VA.getLocInfo() != CCValAssign::Full)
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ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
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ArgValues.push_back(ArgValue);
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}
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} else {
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// Sanity check
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assert(VA.isMemLoc());
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// Load the argument to a virtual register
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unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
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if (ObjSize > 8) {
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cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
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<< VA.getLocVT().getSimpleVT()
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<< "\n";
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}
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// Create the frame index object for this incoming parameter...
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int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset());
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// Create the SelectionDAG nodes corresponding to a load
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//from this parameter
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SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
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ArgValues.push_back(DAG.getLoad(VA.getLocVT(), dl, Root, FIN,
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PseudoSourceValue::getFixedStack(FI), 0));
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}
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}
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ArgValues.push_back(Root);
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// Return the new list of results.
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return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
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&ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
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}
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/// LowerCCCCallTo - functions arguments are copied from virtual regs to
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/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
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/// TODO: sret.
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SDValue SystemZTargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
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unsigned CC) {
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CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
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SDValue Chain = TheCall->getChain();
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SDValue Callee = TheCall->getCallee();
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bool isVarArg = TheCall->isVarArg();
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DebugLoc dl = Op.getDebugLoc();
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// Analyze operands of the call, assigning locations to each operand.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
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CCInfo.AnalyzeCallOperands(TheCall, CC_SystemZ);
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// Get a count of how many bytes are to be pushed on the stack.
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unsigned NumBytes = CCInfo.getNextStackOffset();
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Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
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getPointerTy(), true));
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SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
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SmallVector<SDValue, 12> MemOpChains;
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SDValue StackPtr;
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// Walk the register/memloc assignments, inserting copies/loads.
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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// Arguments start after the 5 first operands of ISD::CALL
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SDValue Arg = TheCall->getArg(i);
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// Promote the value if needed.
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switch (VA.getLocInfo()) {
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default: assert(0 && "Unknown loc info!");
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case CCValAssign::Full: break;
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case CCValAssign::SExt:
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Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
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break;
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case CCValAssign::ZExt:
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Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
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break;
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case CCValAssign::AExt:
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Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
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break;
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}
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// Arguments that can be passed on register must be kept at RegsToPass
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// vector
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if (VA.isRegLoc()) {
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RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
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} else {
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assert(VA.isMemLoc());
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if (StackPtr.getNode() == 0)
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StackPtr = DAG.getCopyFromReg(Chain, dl, SystemZ::R15D, getPointerTy());
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SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
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StackPtr,
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DAG.getIntPtrConstant(VA.getLocMemOffset()));
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MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
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PseudoSourceValue::getStack(),
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VA.getLocMemOffset()));
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}
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}
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// Transform all store nodes into one single node because all store nodes are
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// independent of each other.
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if (!MemOpChains.empty())
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Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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&MemOpChains[0], MemOpChains.size());
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// Build a sequence of copy-to-reg nodes chained together with token chain and
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// flag operands which copy the outgoing args into registers. The InFlag in
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// necessary since all emited instructions must be stuck together.
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SDValue InFlag;
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for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
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Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
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RegsToPass[i].second, InFlag);
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InFlag = Chain.getValue(1);
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}
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// If the callee is a GlobalAddress node (quite common, every direct call is)
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// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
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// Likewise ExternalSymbol -> TargetExternalSymbol.
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
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Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
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else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
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Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
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// Returns a chain & a flag for retval copy to use.
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SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
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SmallVector<SDValue, 8> Ops;
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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// Add argument registers to the end of the list so that they are
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// known live into the call.
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for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
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Ops.push_back(DAG.getRegister(RegsToPass[i].first,
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RegsToPass[i].second.getValueType()));
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if (InFlag.getNode())
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Ops.push_back(InFlag);
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Chain = DAG.getNode(SystemZISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
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InFlag = Chain.getValue(1);
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// Create the CALLSEQ_END node.
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Chain = DAG.getCALLSEQ_END(Chain,
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DAG.getConstant(NumBytes, getPointerTy(), true),
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DAG.getConstant(0, getPointerTy(), true),
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InFlag);
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InFlag = Chain.getValue(1);
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// Handle result values, copying them out of physregs into vregs that we
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// return.
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return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
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Op.getResNo());
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}
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/// LowerCallResult - Lower the result values of an ISD::CALL into the
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/// appropriate copies out of appropriate physical registers. This assumes that
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/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
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/// being lowered. Returns a SDNode with the same number of values as the
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/// ISD::CALL.
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SDNode*
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SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
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CallSDNode *TheCall,
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unsigned CallingConv,
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SelectionDAG &DAG) {
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bool isVarArg = TheCall->isVarArg();
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DebugLoc dl = TheCall->getDebugLoc();
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// Assign locations to each value returned by this call.
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
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CCInfo.AnalyzeCallResult(TheCall, RetCC_SystemZ);
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SmallVector<SDValue, 8> ResultVals;
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// Copy all of the result registers out of their specified physreg.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
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RVLocs[i].getValVT(), InFlag).getValue(1);
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InFlag = Chain.getValue(2);
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ResultVals.push_back(Chain.getValue(0));
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}
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ResultVals.push_back(Chain);
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// Merge everything together with a MERGE_VALUES node.
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return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
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&ResultVals[0], ResultVals.size()).getNode();
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}
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SDValue SystemZTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
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// CCValAssign - represent the assignment of the return value to a location
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SmallVector<CCValAssign, 16> RVLocs;
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unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
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bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
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DebugLoc dl = Op.getDebugLoc();
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// CCState - Info about the registers and stack slot.
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CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
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// Analize return values of ISD::RET
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CCInfo.AnalyzeReturn(Op.getNode(), RetCC_SystemZ);
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// If this is the first return lowered for this function, add the regs to the
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// liveout set for the function.
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if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
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for (unsigned i = 0; i != RVLocs.size(); ++i)
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if (RVLocs[i].isRegLoc())
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DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
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}
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// The chain is always operand #0
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SDValue Chain = Op.getOperand(0);
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SDValue Flag;
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// Copy the result values into the output registers.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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CCValAssign &VA = RVLocs[i];
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SDValue ResValue = Op.getOperand(i*2+1);
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assert(VA.isRegLoc() && "Can only return in registers!");
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// If this is an 8/16/32-bit value, it is really should be passed promoted
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// to 64 bits.
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if (VA.getLocInfo() == CCValAssign::SExt)
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ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);
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else if (VA.getLocInfo() == CCValAssign::ZExt)
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ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);
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else if (VA.getLocInfo() == CCValAssign::AExt)
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ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);
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// ISD::RET => ret chain, (regnum1,val1), ...
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// So i*2+1 index only the regnums
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Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag);
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// Guarantee that all emitted copies are stuck together,
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// avoiding something bad.
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Flag = Chain.getValue(1);
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}
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if (Flag.getNode())
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return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
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// Return Void
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return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain);
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}
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const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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case SystemZISD::RET_FLAG: return "SystemZISD::RET_FLAG";
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case SystemZISD::CALL: return "SystemZISD::CALL";
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default: return NULL;
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}
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}
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