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c2b840cb7c
When loading immediates into a GR32, the port prefered LHI, followed by LLILH or LLILL, followed by IILF. LHI and IILF are natural 32-bit operations, but LLILH and LLILL also clear the upper 32 bits of the register. This was represented as taking a 32-bit subreg of a 64-bit assignment. Using subregs for something as simple as a move immediate was probably a bad idea. Also, I have patches to add support for the high-word facility, and we don't want something like LLILH and LLILL to stop the high word of the same GPR from being used. This patch therefore uses LHI and IILF to begin with and adds a late machine-specific pass to use LLILH and LLILL if the other half of the register is not live. The high-word patches extend this behavior to IIHF, LLIHL and LLIHH. No behavioral change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191363 91177308-0d34-0410-b5e6-96231b3b80d8
69 lines
2.0 KiB
C++
69 lines
2.0 KiB
C++
//===-- SystemZRegisterInfo.h - SystemZ register information ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SystemZREGISTERINFO_H
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#define SystemZREGISTERINFO_H
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#include "SystemZ.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#define GET_REGINFO_HEADER
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#include "SystemZGenRegisterInfo.inc"
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namespace llvm {
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namespace SystemZ {
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// Return the subreg to use for referring to the even and odd registers
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// in a GR128 pair. Is32Bit says whether we want a GR32 or GR64.
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inline unsigned even128(bool Is32bit) {
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return Is32bit ? subreg_32bit : subreg_high;
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}
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inline unsigned odd128(bool Is32bit) {
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return Is32bit ? subreg_low32 : subreg_low;
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}
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}
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class SystemZSubtarget;
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class SystemZInstrInfo;
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struct SystemZRegisterInfo : public SystemZGenRegisterInfo {
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private:
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SystemZTargetMachine &TM;
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public:
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SystemZRegisterInfo(SystemZTargetMachine &tm);
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// Override TargetRegisterInfo.h.
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virtual bool requiresRegisterScavenging(const MachineFunction &MF) const
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LLVM_OVERRIDE {
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return true;
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}
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virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const
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LLVM_OVERRIDE {
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return true;
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}
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virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const
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LLVM_OVERRIDE {
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return true;
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}
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virtual const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0)
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const LLVM_OVERRIDE;
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virtual BitVector getReservedRegs(const MachineFunction &MF)
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const LLVM_OVERRIDE;
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virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const LLVM_OVERRIDE;
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virtual unsigned getFrameRegister(const MachineFunction &MF) const
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LLVM_OVERRIDE;
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};
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} // end namespace llvm
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#endif
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