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https://github.com/c64scene-ar/llvm-6502.git
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a70f28ce7d
The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96969 91177308-0d34-0410-b5e6-96231b3b80d8
71 lines
1.7 KiB
LLVM
71 lines
1.7 KiB
LLVM
; Ensure that all immediate values that are 32-bits or less can be loaded
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; using a single instruction and that immediate values 64-bits or less can
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; be loaded using two instructions.
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;
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; RUN: llc < %s -march=mblaze | FileCheck %s
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; RUN: llc < %s -march=mblaze -mattr=+fpu | FileCheck -check-prefix=FPU %s
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define i8 @retimm_i8() {
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; CHECK: retimm_i8:
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; CHECK: add
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; CHECK-NEXT: rtsd
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; FPU: retimm_i8:
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; FPU: add
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; FPU-NEXT: rtsd
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ret i8 123
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}
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define i16 @retimm_i16() {
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; CHECK: retimm_i16:
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; CHECK: add
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; CHECK-NEXT: rtsd
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; FPU: retimm_i16:
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; FPU: add
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; FPU-NEXT: rtsd
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ret i16 38212
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}
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define i32 @retimm_i32() {
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; CHECK: retimm_i32:
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; CHECK: add
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; CHECK-NEXT: rtsd
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; FPU: retimm_i32:
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; FPU: add
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; FPU-NEXT: rtsd
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ret i32 2938128
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}
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define i64 @retimm_i64() {
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; CHECK: retimm_i64:
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; CHECK: add
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; CHECK-NEXT: add
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; CHECK-NEXT: rtsd
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; FPU: retimm_i64:
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; FPU: add
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; FPU-NEXT: add
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; FPU-NEXT: rtsd
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ret i64 94581823
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}
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define float @retimm_float() {
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; CHECK: retimm_float:
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; CHECK: add
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; CHECK-NEXT: rtsd
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; FPU: retimm_float:
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; FPU: or
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; FPU: rtsd
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ret float 12.0
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}
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define double @retimm_double() {
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; CHECK: retimm_double:
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; CHECK: add
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; CHECK-NEXT: add
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; CHECK-NEXT: rtsd
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; FPU: retimm_double:
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; FPU: add
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; FPU-NEXT: add
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; FPU-NEXT: rtsd
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ret double 598382.39283873
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}
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