mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
0e0f907356
Summary: This required a new instruction group representing the 32-bit subset of MIPS-3 that was available in MIPS32R2. To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3696 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3697 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208690 91177308-0d34-0410-b5e6-96231b3b80d8
308 lines
13 KiB
TableGen
308 lines
13 KiB
TableGen
def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
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def simm12 : Operand<i32> {
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let DecoderMethod = "DecodeSimm12";
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}
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def mem_mm_12 : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops GPR32, simm12);
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let EncoderMethod = "getMemEncodingMMImm12";
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let ParserMatchClass = MipsMemAsmOperand;
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let OperandType = "OPERAND_MEMORY";
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}
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def jmptarget_mm : Operand<OtherVT> {
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let EncoderMethod = "getJumpTargetOpValueMM";
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}
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def calltarget_mm : Operand<iPTR> {
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let EncoderMethod = "getJumpTargetOpValueMM";
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}
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def brtarget_mm : Operand<OtherVT> {
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let EncoderMethod = "getBranchTargetOpValueMM";
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let OperandType = "OPERAND_PCREL";
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let DecoderMethod = "DecodeBranchTargetMM";
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}
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let canFoldAsLoad = 1 in
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class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
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Operand MemOpnd> :
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InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
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!strconcat(opstr, "\t$rt, $addr"),
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[(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
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NoItinerary, FrmI> {
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let DecoderMethod = "DecodeMemMMImm12";
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string Constraints = "$src = $rt";
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}
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class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
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Operand MemOpnd>:
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InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
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!strconcat(opstr, "\t$rt, $addr"),
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[(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
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let DecoderMethod = "DecodeMemMMImm12";
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}
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class LLBaseMM<string opstr, RegisterOperand RO> :
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InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
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!strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
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let DecoderMethod = "DecodeMemMMImm12";
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let mayLoad = 1;
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}
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class SCBaseMM<string opstr, RegisterOperand RO> :
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InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
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!strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
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let DecoderMethod = "DecodeMemMMImm12";
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let mayStore = 1;
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let Constraints = "$rt = $dst";
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}
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class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
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InstrItinClass Itin = NoItinerary> :
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InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
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!strconcat(opstr, "\t$rt, $addr"),
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[(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
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let DecoderMethod = "DecodeMemMMImm12";
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let canFoldAsLoad = 1;
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let mayLoad = 1;
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}
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class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
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MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
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[], II_MFHI_MFLO, FrmR> {
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let Uses = [UseReg];
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let hasSideEffects = 0;
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}
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class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
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InstrItinClass Itin = NoItinerary> :
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MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
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!strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> {
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let isCommutable = isComm;
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let isReMaterializable = 1;
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}
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// 16-bit Jump and Link (Call)
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class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
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MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
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[(MipsJmpLink RO:$rs)], IIBranch, FrmR> {
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let isCall = 1;
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let hasDelaySlot = 1;
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let Defs = [RA];
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}
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def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
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def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
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def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
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def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
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class WaitMM<string opstr> :
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InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
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NoItinerary, FrmOther, opstr>;
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let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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/// Arithmetic Instructions (ALU Immediate)
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def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
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ADDI_FM_MM<0xc>;
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def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
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ADDI_FM_MM<0x4>;
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def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
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SLTI_FM_MM<0x24>;
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def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
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SLTI_FM_MM<0x2c>;
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def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
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ADDI_FM_MM<0x34>;
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def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
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ADDI_FM_MM<0x14>;
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def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
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ADDI_FM_MM<0x1c>;
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def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
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def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
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LW_FM_MM<0xc>;
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/// Arithmetic Instructions (3-Operand, R-Type)
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def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
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def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
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def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
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def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
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def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
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def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
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def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
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ADD_FM_MM<0, 0x390>;
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def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
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ADD_FM_MM<0, 0x250>;
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def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
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ADD_FM_MM<0, 0x290>;
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def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
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ADD_FM_MM<0, 0x310>;
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def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
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def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
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MULT_FM_MM<0x22c>;
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def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
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MULT_FM_MM<0x26c>;
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def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
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MULT_FM_MM<0x2ac>;
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def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
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MULT_FM_MM<0x2ec>;
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/// Shift Instructions
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def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
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SRA_FM_MM<0, 0>;
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def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
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SRA_FM_MM<0x40, 0>;
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def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
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SRA_FM_MM<0x80, 0>;
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def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
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SRLV_FM_MM<0x10, 0>;
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def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
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SRLV_FM_MM<0x50, 0>;
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def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
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SRLV_FM_MM<0x90, 0>;
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def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
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SRA_FM_MM<0xc0, 0>;
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def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
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SRLV_FM_MM<0xd0, 0>;
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/// Load and Store Instructions - aligned
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let DecoderMethod = "DecodeMemMMImm16" in {
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def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
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def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
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def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
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def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
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def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
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def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
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def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
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def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
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}
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def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
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/// Load and Store Instructions - unaligned
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def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
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LWL_FM_MM<0x0>;
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def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
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LWL_FM_MM<0x1>;
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def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
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LWL_FM_MM<0x8>;
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def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
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LWL_FM_MM<0x9>;
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/// Move Conditional
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def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
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NoItinerary>, ADD_FM_MM<0, 0x58>;
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def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
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NoItinerary>, ADD_FM_MM<0, 0x18>;
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def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
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CMov_F_I_FM_MM<0x25>;
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def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
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CMov_F_I_FM_MM<0x5>;
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/// Move to/from HI/LO
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def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
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MTLO_FM_MM<0x0b5>;
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def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
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MTLO_FM_MM<0x0f5>;
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def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
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MFLO_FM_MM<0x035>;
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def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
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MFLO_FM_MM<0x075>;
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/// Multiply Add/Sub Instructions
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def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
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def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
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def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
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def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
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/// Count Leading
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def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>,
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ISA_MIPS32;
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def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>,
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ISA_MIPS32;
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/// Sign Ext In Register Instructions.
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def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
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SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
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def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
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SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
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/// Word Swap Bytes Within Halfwords
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def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>,
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ISA_MIPS32R2;
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def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
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EXT_FM_MM<0x2c>;
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def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
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EXT_FM_MM<0x0c>;
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/// Jump Instructions
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let DecoderMethod = "DecodeJumpTargetMM" in {
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def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
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J_FM_MM<0x35>;
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def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
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}
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def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
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def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
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def RET_MM : MMRel, RetBase<"ret", GPR32Opnd>, JR_FM_MM<0x3c>;
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/// Branch Instructions
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def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
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BEQ_FM_MM<0x25>;
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def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
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BEQ_FM_MM<0x2d>;
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def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
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BGEZ_FM_MM<0x2>;
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def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
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BGEZ_FM_MM<0x6>;
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def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
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BGEZ_FM_MM<0x4>;
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def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
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BGEZ_FM_MM<0x0>;
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def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
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BGEZAL_FM_MM<0x03>;
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def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
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BGEZAL_FM_MM<0x01>;
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/// Control Instructions
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def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
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def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
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def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM;
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def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
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def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
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def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
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def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>,
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ISA_MIPS32R2;
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def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>,
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ISA_MIPS32R2;
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/// Trap Instructions
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def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
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def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
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def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
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def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
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def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
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def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
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def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
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def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
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def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
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def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
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def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
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def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
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/// Load-linked, Store-conditional
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def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
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def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
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}
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//===----------------------------------------------------------------------===//
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// MicroMips instruction aliases
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//===----------------------------------------------------------------------===//
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let Predicates = [InMicroMips] in {
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def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;
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}
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