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https://github.com/c64scene-ar/llvm-6502.git
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36b0fd51de
Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209512 91177308-0d34-0410-b5e6-96231b3b80d8
89 lines
3.5 KiB
TableGen
89 lines
3.5 KiB
TableGen
//=- Mips64r6InstrInfo.td - Mips64r6 Instruction Information -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips64r6 instructions.
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//
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//===----------------------------------------------------------------------===//
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// Notes about removals/changes from MIPS32r6:
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// Reencoded: dclo, dclz
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// Reencoded: lld, scd
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// Removed: daddi
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// Removed: ddiv, ddivu, dmult, dmultu
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// Removed: div, divu
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//===----------------------------------------------------------------------===//
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//
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// Instruction Encodings
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//
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//===----------------------------------------------------------------------===//
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class DALIGN_ENC : SPECIAL3_DALIGN_FM<OPCODE6_DALIGN>;
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class DAUI_ENC : DAUI_FM;
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class DAHI_ENC : REGIMM_FM<OPCODE5_DAHI>;
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class DATI_ENC : REGIMM_FM<OPCODE5_DATI>;
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class DBITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_DBITSWAP>;
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class DDIV_ENC : SPECIAL_3R_FM<0b00010, 0b011110>;
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class DDIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011111>;
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class DMOD_ENC : SPECIAL_3R_FM<0b00011, 0b011110>;
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class DMODU_ENC : SPECIAL_3R_FM<0b00011, 0b011111>;
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class DMUH_ENC : SPECIAL_3R_FM<0b00011, 0b111000>;
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class DMUHU_ENC : SPECIAL_3R_FM<0b00011, 0b111001>;
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class DMUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b111000>;
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class DMULU_ENC : SPECIAL_3R_FM<0b00010, 0b111001>;
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//===----------------------------------------------------------------------===//
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//
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// Instruction Descriptions
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//
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//===----------------------------------------------------------------------===//
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class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
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dag OutOperandList = (outs GPROpnd:$rs);
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dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
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string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
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string Constraints = "$rs = $rt";
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}
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class DALIGN_DESC : ALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>;
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class DAHI_DESC : AHI_ATI_DESC_BASE<"dahi", GPR64Opnd>;
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class DATI_DESC : AHI_ATI_DESC_BASE<"dati", GPR64Opnd>;
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class DAUI_DESC : AUI_DESC_BASE<"daui", GPR64Opnd>;
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class DBITSWAP_DESC : BITSWAP_DESC_BASE<"dbitswap", GPR64Opnd>;
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class DDIV_DESC : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd>;
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class DDIVU_DESC : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd>;
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class DMOD_DESC : DIVMOD_DESC_BASE<"dmod", GPR64Opnd>;
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class DMODU_DESC : DIVMOD_DESC_BASE<"dmodu", GPR64Opnd>;
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class DMUH_DESC : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd>;
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class DMUHU_DESC : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd>;
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class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd>;
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class DMULU_DESC : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd>;
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//===----------------------------------------------------------------------===//
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//
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// Instruction Definitions
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//
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//===----------------------------------------------------------------------===//
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def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
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def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
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def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
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def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
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def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
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def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
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def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
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// def DLSA; // See MSA
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def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
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def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
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def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
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def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
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def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
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def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
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def LDPC;
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