mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201081 91177308-0d34-0410-b5e6-96231b3b80d8
466 lines
9.3 KiB
TableGen
466 lines
9.3 KiB
TableGen
//===- MipsMSAInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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def HasMSA : Predicate<"Subtarget.hasMSA()">,
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AssemblerPredicate<"FeatureMSA">;
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class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
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let Predicates = [HasMSA];
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let Inst{31-26} = 0b011110;
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}
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class MSA64Inst : MSAInst {
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let Predicates = [HasMSA, HasMips64];
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}
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class MSACBranch : MSAInst {
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let Inst{31-26} = 0b010001;
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}
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class MSASpecial : MSAInst {
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let Inst{31-26} = 0b000000;
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}
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class MSA64Special : MSA64Inst {
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let Inst{31-26} = 0b000000;
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}
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class MSAPseudo<dag outs, dag ins, list<dag> pattern,
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InstrItinClass itin = IIPseudo>:
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MipsPseudo<outs, ins, pattern, itin> {
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let Predicates = [HasMSA];
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}
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class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
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bits<5> ws;
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bits<5> wd;
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bits<3> m;
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let Inst{25-23} = major;
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let Inst{22-19} = 0b1110;
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let Inst{18-16} = m;
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {
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bits<5> ws;
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bits<5> wd;
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bits<4> m;
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let Inst{25-23} = major;
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let Inst{22-20} = 0b110;
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let Inst{19-16} = m;
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {
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bits<5> ws;
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bits<5> wd;
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bits<5> m;
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let Inst{25-23} = major;
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let Inst{22-21} = 0b10;
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let Inst{20-16} = m;
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_BIT_D_FMT<bits<3> major, bits<6> minor>: MSAInst {
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bits<5> ws;
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bits<5> wd;
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bits<6> m;
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let Inst{25-23} = major;
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let Inst{22} = 0b0;
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let Inst{21-16} = m;
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_2R_FILL_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
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bits<5> rs;
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bits<5> wd;
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let Inst{25-18} = major;
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let Inst{17-16} = df;
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let Inst{15-11} = rs;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_2R_FILL_D_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSA64Inst {
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bits<5> rs;
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bits<5> wd;
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let Inst{25-18} = major;
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let Inst{17-16} = df;
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let Inst{15-11} = rs;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_2R_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
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bits<5> ws;
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bits<5> wd;
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let Inst{25-18} = major;
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let Inst{17-16} = df;
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_2RF_FMT<bits<9> major, bits<1> df, bits<6> minor>: MSAInst {
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bits<5> ws;
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bits<5> wd;
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let Inst{25-17} = major;
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let Inst{16} = df;
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_3R_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
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bits<5> wt;
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bits<5> ws;
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bits<5> wd;
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let Inst{25-23} = major;
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let Inst{22-21} = df;
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let Inst{20-16} = wt;
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_3RF_FMT<bits<4> major, bits<1> df, bits<6> minor>: MSAInst {
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bits<5> wt;
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bits<5> ws;
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bits<5> wd;
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let Inst{25-22} = major;
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let Inst{21} = df;
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let Inst{20-16} = wt;
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_3R_INDEX_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
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bits<5> rt;
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bits<5> ws;
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bits<5> wd;
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let Inst{25-23} = major;
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let Inst{22-21} = df;
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let Inst{20-16} = rt;
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_ELM_FMT<bits<10> major, bits<6> minor>: MSAInst {
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bits<5> ws;
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bits<5> wd;
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let Inst{25-16} = major;
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_ELM_CFCMSA_FMT<bits<10> major, bits<6> minor>: MSAInst {
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bits<5> rd;
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bits<5> cs;
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let Inst{25-16} = major;
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let Inst{15-11} = cs;
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let Inst{10-6} = rd;
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let Inst{5-0} = minor;
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}
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class MSA_ELM_CTCMSA_FMT<bits<10> major, bits<6> minor>: MSAInst {
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bits<5> rs;
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bits<5> cd;
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let Inst{25-16} = major;
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let Inst{15-11} = rs;
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let Inst{10-6} = cd;
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let Inst{5-0} = minor;
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}
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class MSA_ELM_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
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bits<4> n;
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bits<5> ws;
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bits<5> wd;
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let Inst{25-22} = major;
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let Inst{21-20} = 0b00;
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let Inst{19-16} = n{3-0};
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_ELM_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
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bits<4> n;
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bits<5> ws;
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bits<5> wd;
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let Inst{25-22} = major;
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let Inst{21-19} = 0b100;
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let Inst{18-16} = n{2-0};
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_ELM_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
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bits<4> n;
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bits<5> ws;
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bits<5> wd;
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let Inst{25-22} = major;
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let Inst{21-18} = 0b1100;
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let Inst{17-16} = n{1-0};
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_ELM_D_FMT<bits<4> major, bits<6> minor>: MSAInst {
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bits<4> n;
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bits<5> ws;
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bits<5> wd;
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let Inst{25-22} = major;
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let Inst{21-17} = 0b11100;
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let Inst{16} = n{0};
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_ELM_COPY_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
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bits<4> n;
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bits<5> ws;
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bits<5> rd;
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let Inst{25-22} = major;
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let Inst{21-20} = 0b00;
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let Inst{19-16} = n{3-0};
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let Inst{15-11} = ws;
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let Inst{10-6} = rd;
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let Inst{5-0} = minor;
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}
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class MSA_ELM_COPY_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
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bits<4> n;
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bits<5> ws;
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bits<5> rd;
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let Inst{25-22} = major;
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let Inst{21-19} = 0b100;
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let Inst{18-16} = n{2-0};
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let Inst{15-11} = ws;
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let Inst{10-6} = rd;
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let Inst{5-0} = minor;
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}
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class MSA_ELM_COPY_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
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bits<4> n;
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bits<5> ws;
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bits<5> rd;
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let Inst{25-22} = major;
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let Inst{21-18} = 0b1100;
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let Inst{17-16} = n{1-0};
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let Inst{15-11} = ws;
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let Inst{10-6} = rd;
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let Inst{5-0} = minor;
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}
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class MSA_ELM_COPY_D_FMT<bits<4> major, bits<6> minor>: MSA64Inst {
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bits<4> n;
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bits<5> ws;
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bits<5> rd;
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let Inst{25-22} = major;
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let Inst{21-17} = 0b11100;
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let Inst{16} = n{0};
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let Inst{15-11} = ws;
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let Inst{10-6} = rd;
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let Inst{5-0} = minor;
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}
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class MSA_ELM_INSERT_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
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bits<6> n;
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bits<5> rs;
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bits<5> wd;
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let Inst{25-22} = major;
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let Inst{21-20} = 0b00;
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let Inst{19-16} = n{3-0};
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let Inst{15-11} = rs;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_ELM_INSERT_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
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bits<6> n;
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bits<5> rs;
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bits<5> wd;
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let Inst{25-22} = major;
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let Inst{21-19} = 0b100;
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let Inst{18-16} = n{2-0};
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let Inst{15-11} = rs;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_ELM_INSERT_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
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bits<6> n;
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bits<5> rs;
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bits<5> wd;
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let Inst{25-22} = major;
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let Inst{21-18} = 0b1100;
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let Inst{17-16} = n{1-0};
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let Inst{15-11} = rs;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_ELM_INSERT_D_FMT<bits<4> major, bits<6> minor>: MSA64Inst {
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bits<6> n;
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bits<5> rs;
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bits<5> wd;
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let Inst{25-22} = major;
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let Inst{21-17} = 0b11100;
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let Inst{16} = n{0};
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let Inst{15-11} = rs;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_I5_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
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bits<5> imm;
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bits<5> ws;
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bits<5> wd;
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let Inst{25-23} = major;
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let Inst{22-21} = df;
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let Inst{20-16} = imm;
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_I8_FMT<bits<2> major, bits<6> minor>: MSAInst {
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bits<8> u8;
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bits<5> ws;
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bits<5> wd;
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let Inst{25-24} = major;
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let Inst{23-16} = u8;
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_I10_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
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bits<10> s10;
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bits<5> wd;
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let Inst{25-23} = major;
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let Inst{22-21} = df;
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let Inst{20-11} = s10;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_MI10_FMT<bits<2> df, bits<4> minor>: MSAInst {
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bits<21> addr;
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bits<5> wd;
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let Inst{25-16} = addr{9-0};
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let Inst{15-11} = addr{20-16};
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let Inst{10-6} = wd;
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let Inst{5-2} = minor;
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let Inst{1-0} = df;
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}
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class MSA_VEC_FMT<bits<5> major, bits<6> minor>: MSAInst {
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bits<5> wt;
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bits<5> ws;
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bits<5> wd;
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let Inst{25-21} = major;
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let Inst{20-16} = wt;
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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class MSA_CBRANCH_FMT<bits<3> major, bits<2> df>: MSACBranch {
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bits<16> offset;
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bits<5> wt;
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let Inst{25-23} = major;
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let Inst{22-21} = df;
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let Inst{20-16} = wt;
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let Inst{15-0} = offset;
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}
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class MSA_CBRANCH_V_FMT<bits<5> major>: MSACBranch {
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bits<16> offset;
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bits<5> wt;
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let Inst{25-21} = major;
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let Inst{20-16} = wt;
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let Inst{15-0} = offset;
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}
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class SPECIAL_LSA_FMT<bits<6> minor>: MSASpecial {
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bits<5> rs;
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bits<5> rt;
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bits<5> rd;
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bits<2> sa;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-8} = 0b000;
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let Inst{7-6} = sa;
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let Inst{5-0} = minor;
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}
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class SPECIAL_DLSA_FMT<bits<6> minor>: MSA64Special {
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bits<5> rs;
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bits<5> rt;
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bits<5> rd;
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bits<2> sa;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-8} = 0b000;
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let Inst{7-6} = sa;
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let Inst{5-0} = minor;
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}
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